#24242 - More patches (TGA server this time)

Debian Bug report logs - #24242
More patches (TGA server this time)

Reported by: Anders Hammarquist <iko@netg.se>

Date: Sat, 4 Jul 1998 16:18:01 UTC

Severity: normal

Done: branden@indy.progenylinux.com (Branden Robinson)

Bug is archived. No further changes may be made.

Report forwarded to debian-bugs-dist@lists.debian.org, Branden Robinson <branden@debian.org>:
Bug#24242; Package xserver-tga. (full text, mbox, link).

Acknowledgement sent to Anders Hammarquist <iko@netg.se>:
New bug report received and forwarded. Copy sent to Branden Robinson <branden@debian.org>. (full text, mbox, link).

Message #5 received at submit@bugs.debian.org (full text, mbox, reply):

Package: xserver-tga Version: 3.3.2.2-1 Chris Chimelis pointed me to these patches for the TGA server which are supposed to make it talk to a few more of the TGA cards. They are in my -1.2 NMU of xserver-tga. (patches from http://www.cs.brown.edu/~tor/xfree86 /tga-patch-980704.gz /Anders diff -u xc/programs/Xserver/hw/xfree86/accel/tga-orig/tga.c xc/programs/Xserver/hw/xfree86/accel/tga/tga.c --- xc/programs/Xserver/hw/xfree86/accel/tga-orig/tga.c Mon Mar 2 06:55:33 1998 +++ xc/programs/Xserver/hw/xfree86/accel/tga/tga.c Fri Jul 3 14:42:22 1998 @@ -44,6 +44,7 @@ #include "tga_presets.h" #include "xf86xaa.h" +#include "xf86scrin.h" #define XCONFIG_FLAGS_ONLY #include "xf86_Config.h" @@ -62,6 +63,8 @@ #include "extensions/dpms.h" #endif +extern int defaultColorVisualClass; + static int tgaValidMode( #if NeedFunctionPrototypes DisplayModePtr, @@ -273,14 +276,10 @@ case TYPE_TGA_24PLANE: ErrorF("%s %s: DEC 21030 TGA 24 Plane Chip Found.\n", XCONFIG_PROBED, tgaInfoRec.name); - ErrorF("Sorry, but the 24 Plane Chip is not yet supported.\n"); - return(FALSE); break; case TYPE_TGA_24PLUSZ: ErrorF("%s %s: DEC 21030 TGA 24 Plane 3D Chip Found.\n", XCONFIG_PROBED, tgaInfoRec.name); - ErrorF("Sorry, but the 24Plane3D Chip is not yet supported.\n"); - return(FALSE); break; default: ErrorF("%s %s: OUCH ! Found an unknown TGA Chip. Aborting..\n", @@ -289,9 +288,26 @@ break; } + if ((tga_type == TYPE_TGA_24PLANE) || (tga_type == TYPE_TGA_24PLUSZ)) { + tgaInfoRec.depth = 24; + tgaInfoRec.bitsPerPixel = 32; + tgaInfoRec.defaultVisual = TrueColor; + defaultColorVisualClass = TrueColor; + } + if (tgaInfoRec.videoRam == 0) { - tgaInfoRec.videoRam = 2048; + switch (tga_type) { + case TYPE_TGA_8PLANE: + tgaInfoRec.videoRam = 2*1024; + break; + case TYPE_TGA_24PLANE: + tgaInfoRec.videoRam = 8*1024; + break; + case TYPE_TGA_24PLUSZ: + tgaInfoRec.videoRam = 16*1024; + break; + } ErrorF("%s %s: videoram : %dk\n", XCONFIG_PROBED, tgaInfoRec.name, tgaInfoRec.videoRam); } @@ -428,14 +444,27 @@ xf86bpp = tgaInfoRec.depth; if (xf86weight.red == 0 || xf86weight.green == 0 || xf86weight.blue == 0) xf86weight = tgaInfoRec.weight; - switch (xf86bpp) { - case 8: - /* XAA uses this */ - xf86weight.green = (tgaDAC8Bit ? 8 : 6); - break; - default: - ErrorF("Invalid value for bpp. 8bpp is only supported.\n"); - return(FALSE); + + if (tga_type == 0) { /* 8-plane */ + switch (xf86bpp) { + case 8: + /* XAA uses this */ + xf86weight.green = (tgaDAC8Bit ? 8 : 6); + break; + default: + ErrorF("Invalid value for bpp. 8bpp is only supported.\n"); + return(FALSE); + } + } else { + switch (xf86bpp) { + case 32: + /* XAA uses this */ + xf86weight.red = xf86weight.green = xf86weight.blue = 8; + break; + default: + ErrorF("Invalid value for bpp. 32bpp is only supported.\n"); + return(FALSE); + } } #ifdef XFreeXDGA @@ -462,6 +491,7 @@ int displayResolution = 75; /* default to 75dpi */ int i; extern int monitorResolution; + Bool (*ScreenInitFunc)(register ScreenPtr, pointer, int, int, int, int, int); /* Init the screen */ @@ -485,7 +515,12 @@ /* Let's use the new XAA Architecture.....*/ TGAAccelInit(); - if (!xf86XAAScreenInit8bpp(pScreen, + if (tgaInfoRec.bitsPerPixel == 8) + ScreenInitFunc = &xf86XAAScreenInit8bpp; + else + ScreenInitFunc = &xf86XAAScreenInit32bpp; + + if (!ScreenInitFunc(pScreen, #else if (!cfbScreenInit(pScreen, #endif diff -u xc/programs/Xserver/hw/xfree86/accel/tga-orig/tga_regs.h xc/programs/Xserver/hw/xfree86/accel/tga/tga_regs.h --- xc/programs/Xserver/hw/xfree86/accel/tga-orig/tga_regs.h Sun Jan 5 06:54:33 1997 +++ xc/programs/Xserver/hw/xfree86/accel/tga/tga_regs.h Fri Jul 3 17:42:09 1998 @@ -51,6 +51,17 @@ TGA_WRITE_REG((r),TGA_RAMDAC_SETUP_REG); \ TGA_WRITE_REG(((v)&0xff)|((r)<<8),TGA_RAMDAC_REG); +#define BT463_LOAD_ADDR(a) \ + TGA_WRITE_REG(BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG); \ + TGA_WRITE_REG((BT463_ADDR_LO<<10)|((a)&0xff), TGA_RAMDAC_REG); \ + TGA_WRITE_REG(BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG); \ + TGA_WRITE_REG((BT463_ADDR_HI<<10)|(((a)>>8)&0xff), TGA_RAMDAC_REG); + +#define BT463_WRITE(m,a,v) \ + BT463_LOAD_ADDR((a)); \ + TGA_WRITE_REG(((m)<<2),TGA_RAMDAC_SETUP_REG); \ + TGA_WRITE_REG(((m)<<10)|((v)&0xff),TGA_RAMDAC_REG); + #define mb() \ __asm__ __volatile__("mb": : :"memory") @@ -127,6 +138,8 @@ /* * useful defines for managing the BT463 on the 24-plane TGAs */ +#define BT463_READ_BIT 0x2 + #define BT463_ADDR_LO 0x0 #define BT463_ADDR_HI 0x1 #define BT463_REG_ACC 0x2 diff -u xc/programs/Xserver/hw/xfree86/accel/tga-orig/tgainit.c xc/programs/Xserver/hw/xfree86/accel/tga/tgainit.c --- xc/programs/Xserver/hw/xfree86/accel/tga-orig/tgainit.c Fri Dec 27 02:03:52 1996 +++ xc/programs/Xserver/hw/xfree86/accel/tga/tgainit.c Sat Jul 4 01:36:30 1998 @@ -30,6 +30,8 @@ typedef struct { unsigned long Bt485[0x20]; unsigned long tgaRegs[0x200]; + unsigned long Bt463[0x20]; + unsigned long Bt463win[48]; } tgaRegisters; static tgaRegisters SR; @@ -101,20 +103,59 @@ TGA_WRITE_REG(0x05, TGA_VALID_REG); /* Enable Video */ } + +unsigned +BT463_READ(unsigned m, unsigned a) +{ + unsigned val; + + BT463_LOAD_ADDR(a); + TGA_WRITE_REG((m<<2)|0x2, TGA_RAMDAC_SETUP_REG); + val = TGA_READ_REG(TGA_RAMDAC_REG); + val = (val >> 16) & 0xff; + return val; +} + + void saveTGAstate() { - int i; + int i, j; /* Do the RAMDAC */ - TGA_WRITE_REG(BT485_CMD_0, TGA_RAMDAC_SETUP_REG); - SR.Bt485[0] = TGA_READ_REG(TGA_RAMDAC_REG); - TGA_WRITE_REG(BT485_CMD_1, TGA_RAMDAC_SETUP_REG); - SR.Bt485[1] = TGA_READ_REG(TGA_RAMDAC_REG); - TGA_WRITE_REG(BT485_CMD_2, TGA_RAMDAC_SETUP_REG); - SR.Bt485[2] = TGA_READ_REG(TGA_RAMDAC_REG); - TGA_WRITE_REG(BT485_CMD_3, TGA_RAMDAC_SETUP_REG); - SR.Bt485[3] = TGA_READ_REG(TGA_RAMDAC_REG); + if (tga_type == 0) { /* 8-plane */ + TGA_WRITE_REG(BT485_CMD_0, TGA_RAMDAC_SETUP_REG); + SR.Bt485[0] = TGA_READ_REG(TGA_RAMDAC_REG); + TGA_WRITE_REG(BT485_CMD_1, TGA_RAMDAC_SETUP_REG); + SR.Bt485[1] = TGA_READ_REG(TGA_RAMDAC_REG); + TGA_WRITE_REG(BT485_CMD_2, TGA_RAMDAC_SETUP_REG); + SR.Bt485[2] = TGA_READ_REG(TGA_RAMDAC_REG); + TGA_WRITE_REG(BT485_CMD_3, TGA_RAMDAC_SETUP_REG); + SR.Bt485[3] = TGA_READ_REG(TGA_RAMDAC_REG); + } else { + SR.Bt463[0] = BT463_READ(BT463_REG_ACC, BT463_CMD_REG_0); + SR.Bt463[1] = BT463_READ(BT463_REG_ACC, BT463_CMD_REG_1); + SR.Bt463[2] = BT463_READ(BT463_REG_ACC, BT463_CMD_REG_2); + + SR.Bt463[3] = BT463_READ(BT463_REG_ACC, BT463_READ_MASK_0); + SR.Bt463[4] = BT463_READ(BT463_REG_ACC, BT463_READ_MASK_1); + SR.Bt463[5] = BT463_READ(BT463_REG_ACC, BT463_READ_MASK_2); + SR.Bt463[6] = BT463_READ(BT463_REG_ACC, BT463_READ_MASK_3); + + SR.Bt463[7] = BT463_READ(BT463_REG_ACC, BT463_BLINK_MASK_0); + SR.Bt463[8] = BT463_READ(BT463_REG_ACC, BT463_BLINK_MASK_1); + SR.Bt463[9] = BT463_READ(BT463_REG_ACC, BT463_BLINK_MASK_2); + SR.Bt463[10] = BT463_READ(BT463_REG_ACC, BT463_BLINK_MASK_3); + + BT463_LOAD_ADDR(BT463_WINDOW_TYPE_BASE); + TGA_WRITE_REG((BT463_REG_ACC<<2)|0x2, TGA_RAMDAC_SETUP_REG); + + for (i = 0, j = 0; i < 16; i++) { + SR.Bt463win[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff; + SR.Bt463win[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff; + SR.Bt463win[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff; + } + } SR.tgaRegs[0] = TGA_READ_REG(TGA_HORIZ_REG); SR.tgaRegs[1] = TGA_READ_REG(TGA_VERT_REG); @@ -153,6 +194,33 @@ ICS1562ClockSelect(25175); TGA_WRITE_REG(SR.tgaRegs[2], TGA_VALID_REG); /* Re-enable Video */ + + if (tga_type != 0) { + int i, j; + + BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_0, SR.Bt463[0]); + BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_1, SR.Bt463[1]); + BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_2, SR.Bt463[2]); + + BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_0, SR.Bt463[3]); + BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_1, SR.Bt463[4]); + BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_2, SR.Bt463[5]); + BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_3, SR.Bt463[6]); + + BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_0, SR.Bt463[7]); + BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_1, SR.Bt463[8]); + BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_2, SR.Bt463[9]); + BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_3, SR.Bt463[10]); + + BT463_LOAD_ADDR(BT463_WINDOW_TYPE_BASE); + TGA_WRITE_REG((BT463_REG_ACC<<2), TGA_RAMDAC_SETUP_REG); + + for (i = 0, j = 0; i < 16; i++) { + TGA_WRITE_REG(SR.Bt463win[j++]|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); + TGA_WRITE_REG(SR.Bt463win[j++]|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); + TGA_WRITE_REG(SR.Bt463win[j++]|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); + } + } } @@ -211,6 +279,39 @@ BT485_WRITE(0xFF, BT485_PIXEL_MASK); } +void +#if NeedFunctionPrototypes +BT463Enable(void) +#else +BT463Enable() +#endif +{ + int i; + + BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_0, 0x40); + BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_1, 0x00); + BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_2, 0x40); + + BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_0, 0xff); + BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_1, 0xff); + BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_2, 0xff); + BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_3, 0x0f); + + BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00); + BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00); + BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00); + BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00); + + BT463_LOAD_ADDR(BT463_WINDOW_TYPE_BASE); + TGA_WRITE_REG((BT463_REG_ACC<<2), TGA_RAMDAC_SETUP_REG); + + for (i = 0; i < 16; i++) { + TGA_WRITE_REG(0x00|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); + TGA_WRITE_REG(0x01|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); + TGA_WRITE_REG(0x80|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); + } +} + #if NeedFunctionPrototypes static void InitLUT(void) @@ -221,28 +322,58 @@ { int i; - /* Get BT485's pallette */ - BT485_WRITE(0x00, BT485_ADDR_PAL_WRITE); - TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); - - for (i=0; i<256; i++) { - oldlut[i].r = TGA_READ_REG(TGA_RAMDAC_REG); - oldlut[i].g = TGA_READ_REG(TGA_RAMDAC_REG); - oldlut[i].b = TGA_READ_REG(TGA_RAMDAC_REG); - } + if (tga_type == 0) { /* 8-plane */ - for (i=0; i<16; i++) { - TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); - TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); - TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); - } + /* Get BT485's pallette */ + BT485_WRITE(0x00, BT485_ADDR_PAL_WRITE); + TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); + + for (i=0; i<256; i++) { + oldlut[i].r = TGA_READ_REG(TGA_RAMDAC_REG); + oldlut[i].g = TGA_READ_REG(TGA_RAMDAC_REG); + oldlut[i].b = TGA_READ_REG(TGA_RAMDAC_REG); + } - for (i=0; i<720; i+=4) { + for (i=0; i<16; i++) { + TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); + TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); + TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); + } + + for (i=0; i<720; i+=4) { TGA_WRITE_REG(0x55|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); - } + } + + } else { + /* Running in TrueColor... we don't need this, do we? -tor */ +#if 0 + /* Get BT463's pallette */ + BT463_LOAD_ADDR(0x0000); + TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG); + + for (i=0; i<256; i++) { + oldlut[i].r = TGA_READ_REG(TGA_RAMDAC_REG); + oldlut[i].g = TGA_READ_REG(TGA_RAMDAC_REG); + oldlut[i].b = TGA_READ_REG(TGA_RAMDAC_REG); + } + + for (i=0; i<16; i++) { + TGA_WRITE_REG(0x00|(BT463_PALETTE<<10),TGA_RAMDAC_REG); + TGA_WRITE_REG(0x00|(BT463_PALETTE<<10),TGA_RAMDAC_REG); + TGA_WRITE_REG(0x00|(BT463_PALETTE<<10),TGA_RAMDAC_REG); + } + + for (i=0; i<720; i+=4) { + TGA_WRITE_REG(0x55|(BT463_PALETTE<<10),TGA_RAMDAC_REG); + TGA_WRITE_REG(0x00|(BT463_PALETTE<<10),TGA_RAMDAC_REG); + TGA_WRITE_REG(0x00|(BT463_PALETTE<<10),TGA_RAMDAC_REG); + TGA_WRITE_REG(0x00|(BT463_PALETTE<<10),TGA_RAMDAC_REG); + } +#endif + } LUTInited = TRUE; } @@ -258,10 +389,8 @@ { if (tga_type == TYPE_TGA_8PLANE) BT485Enable(); -#ifdef SUPPORT24 else BT463Enable(); -#endif InitLUT(); } -- -- Of course I'm crazy, but that doesn't mean I'm wrong. Anders Hammarquist | Mud at Kingdoms | iko@netg.se NetGuide Scandinavia | telnet kingdoms.se 1812 | Fax: +46 31 50 79 39 http://www.netg.se | | Tel: +46 31 50 79 40

Bug reassigned from package `xserver-tga' to `xserver-common'. Request was from "J.H.M. Dassen (Ray)" <jdassen@wi.leidenuniv.nl> to control@bugs.debian.org. (full text, mbox, link).

Reply sent to branden@indy.progenylinux.com (Branden Robinson):
You have taken responsibility. (full text, mbox, link).

Notification sent to Anders Hammarquist <iko@netg.se>:
Bug acknowledged by developer. (full text, mbox, link).

Message #12 received at 24242-done@bugs.debian.org (full text, mbox, reply):

These patches (or equivalent ones) appear to be present upstream from a quick look at the sources. If this is incorrect, please re-file this bug against xserver-xfree86 after testing version 4.0.1 of this package. -- Branden Robinson | GPG signed/encrypted mail welcome branden@progeny.com | 1024D/32222732 Senior Software Developer | E31E 8D74 4BFA 77C9 6560 Progeny Linux Systems | 0560 137B F214 3222 2732

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Debian Bug report logs - #24242 More patches (TGA server this time)

Debian Bug report logs - #24242
More patches (TGA server this time)