xserver-xorg-video-intel: Changes to 'debian-unstable'
debian/changelog | 18 +++++++++++++++
src/common.h | 34 +++++++++++++++++++++++------
src/i810_driver.c | 20 ++++++++++++++---
src/i810_reg.h | 5 ++++
src/i830_display.c | 20 ++++++++++++++---
src/i830_driver.c | 59 +++++++++++++++++++++++++++++++++++++++++-----------
src/i830_lvds.c | 10 +++++---
src/i830_memory.c | 13 ++++++-----
src/i830_quirks.c | 25 +++++++++++++++++-----
src/i830_video.c | 2 -
src/i965_render.c | 2 -
src/i965_video.c | 2 -
src/xvmc/I810XvMC.c | 2 -
13 files changed, 166 insertions(+), 46 deletions(-)
New commits:
commit 32cfad5aed89a96e9ebdfdf653e32daa259b8a04
Author: Julien Cristau <jcristau@debian.org>
Date: Sun Jul 27 02:03:57 2008 +0200
update changelog for cherry-picked patches
diff --git a/debian/changelog b/debian/changelog
index 3d4a51d..4d7bff0 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,21 @@
+xserver-xorg-video-intel (2:2.3.2-2+lenny1) UNRELEASED; urgency=low
+
+ * Cherry-pick patches from the 2.4.0 release:
+ - Add support for Intel 4 series chipsets
+ - add some quirks to force enable pipe A on some machines (in particular,
+ all 855GM)
+ - i810: Remove an effectively unused variable (only used in an incorrect
+ free())
+ - Give asus and eeepc backlight method higher priority
+ - Don't use the phase shift bits on GM45
+ - Fix official name for GM45 chipset
+ - Improve FBC size checking
+ - Only initialize integrated TV encoder for mobile chips
+ - Add no LVDS quirk for Transtec Senyo 610 mini PC
+ - Thinkpad R60e TV quirk via DMI info
+
+ -- Julien Cristau <jcristau@debian.org> Sun, 27 Jul 2008 01:49:09 +0200
+
xserver-xorg-video-intel (2:2.3.2-2) unstable; urgency=high
* High urgency upload for RC bug fix.
commit 81c66dc013f1fc602dc0fb114a64bdf8e99c1e70
Author: Zhenyu Wang <zhenyu.z.wang@intel.com>
Date: Tue Jul 22 09:51:54 2008 +0800
Thinkpad R60e TV quirk via DMI info
(cherry picked from commit b7765b0837af4cc80f1257ba04495140ef5d536e)
(cherry picked from commit 06c5a72a496fabace408fbb8733f299a408d1c7c)
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 164a70c..5ae2898 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -203,7 +203,8 @@ static void quirk_lenovo_tv_dmi (I830Ptr pI830)
ErrorF("Failed to load DMI info, X60 TV quirk not applied.\n");
return;
}
- if (!strncmp(i830_dmi_data[bios_version], "7B", 2))
+ if (!strncmp(i830_dmi_data[bios_version], "7B", 2) || /* X60, X60s */
+ !strncmp(i830_dmi_data[bios_version], "7E", 2)) /* R60e */
pI830->quirk_flag |= QUIRK_IGNORE_TV;
}
commit c41fd34db7d1121e825d3646ac4d4ac4cd17a01c
Author: Jesse Barnes <jbarnes@hobbes.lan>
Date: Mon Jul 21 11:48:38 2008 -0700
Add no LVDS quirk for Transtec Senyo 610 mini PC
Fixes FDO #16757.
(cherry picked from commit ed0fbd016b8fbcf01eddfd17fd25e745e7af2ba4)
(cherry picked from commit 13959ee3984d5f34c976287c8f5406393ceacc30)
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 3becf35..164a70c 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -222,6 +222,9 @@ static i830_quirk i830_quirk_list[] = {
/* Apple Mac mini has no lvds, but macbook pro does */
{ PCI_CHIP_I945_GM, 0x8086, 0x7270, quirk_mac_mini },
+ /* Transtec Senyo 610 mini pc */
+ { PCI_CHIP_I965_GM, 0x1509, 0x2f15, quirk_ignore_lvds },
+
/* Clevo M720R has no tv output */
{ PCI_CHIP_I965_GM, 0x1558, 0x0721, quirk_ignore_tv },
commit b25aefae388cdbf34d2ffa323853cd0661cd40ac
Author: Jesse Barnes <jbarnes@hobbes.lan>
Date: Thu Jul 17 12:30:57 2008 -0700
Don't disable pipe A on 855 chips
It needs to stay enabled or we may see hangs when trying to re-enable it (say
at VT switch time).
Fixes FDO bug #15168.
(cherry picked from commit b37a2a8ca82279468e3806dcf77d5fa7bdd0e874)
(cherry picked from commit 91cbb5b8ad1fbc22dd77c0329fc3962b1ca99b9e)
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 5eb01be..3becf35 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -309,6 +309,9 @@ static i830_quirk i830_quirk_list[] = {
/* Littlebit Sepia X35 (rebranded Asus Z37E) (See LP: #201257) */
{ PCI_CHIP_I965_GM, 0x1043, 0x8265, quirk_ignore_tv },
+ /* 855 & before need to leave pipe A & dpll A up */
+ { PCI_CHIP_I855_GM, SUBSYS_ANY, SUBSYS_ANY, quirk_pipea_force },
+
{ 0, 0, 0, NULL },
};
@@ -325,9 +328,10 @@ void i830_fixup_devices(ScrnInfoPtr scrn)
while (p && p->chipType != 0) {
if (DEVICE_ID(pI830->PciInfo) == p->chipType &&
- SUBVENDOR_ID(pI830->PciInfo) == p->subsysVendor &&
- (SUBSYS_ID(pI830->PciInfo) == p->subsysCard ||
- p->subsysCard == SUBSYS_ANY))
+ (SUBVENDOR_ID(pI830->PciInfo) == p->subsysVendor ||
+ p->subsysVendor == SUBSYS_ANY) &&
+ (SUBSYS_ID(pI830->PciInfo) == p->subsysCard ||
+ p->subsysCard == SUBSYS_ANY))
p->hook(pI830);
++p;
}
commit 4c67765f98a231e8340804d8007ba719d50339cb
Author: Zhenyu Wang <zhenyu.z.wang@intel.com>
Date: Wed Jul 16 10:45:28 2008 +0800
Only initialize integrated TV encoder for mobile chips
(cherry picked from commit c4565a9811487402d899d0933cc63e27ffe1ff08)
(cherry picked from commit a0e7b79b34940d646949512bd24c96372031888d)
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 6ad7089..6121b42 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -929,7 +929,7 @@ I830SetupOutputs(ScrnInfoPtr pScrn)
} else {
i830_dvo_init(pScrn);
}
- if (IS_I9XX(pI830) && !IS_I915G(pI830))
+ if (IS_I9XX(pI830) && IS_MOBILE(pI830))
i830_tv_init(pScrn);
for (o = 0; o < config->num_output; o++)
commit 50ab33dfc7ee18177a23ec57345e32747d92594b
Author: Jesse Barnes <jbarnes@jbarnes-t61.(none)>
Date: Mon Jul 7 10:48:56 2008 -0700
Improve FBC size checking
In hindsight, this is obvious, since nowhere do we tell the FBC unit how much
memory it has available. We need to make sure the compressed buffer is big
enough to handle the uncompresed buffer, both in terms of vertical size and
total framebuffer size, or the compressor could overwrite the memory
immediately following the compressed buffer.
(cherry picked from commit 7332132a79e5b5c208d43e93dfe0c8b12eb1728d)
(cherry picked from commit 7d1aa118a24195833466a4a4342c71f37db673f8)
diff --git a/src/i830_display.c b/src/i830_display.c
index ba6de3a..00577db 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -692,6 +692,7 @@ i830_use_fb_compression(xf86CrtcPtr crtc)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+ unsigned long uncompressed_size;
int plane = (intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
int i, count = 0;
@@ -723,6 +724,19 @@ i830_use_fb_compression(xf86CrtcPtr crtc)
pScrn->bitsPerPixel == 32)) /* mode_set dtrt if fbc is in use */
return FALSE;
+ /* Can't cache more lines than we can track */
+ if (crtc->mode.VDisplay > FBC_LL_SIZE)
+ return FALSE;
+
+ /*
+ * Make sure the compressor doesn't go past the end of our compressed
+ * buffer if the uncompressed size is large.
+ */
+ uncompressed_size = crtc->mode.HDisplay * crtc->mode.VDisplay *
+ pI830->cpp;
+ if (pI830->compressed_front_buffer->size < uncompressed_size)
+ return FALSE;
+
/*
* No checks for pixel multiply, incl. horizontal, or interlaced modes
* since they're currently unused.
commit cc80c042628609dfcba4619f0d4d46bf77d15832
Author: Stefan Dirsch <sndirsch@suse.de>
Date: Thu Jul 3 23:12:13 2008 +0200
Add pipea force enable quirk for another 855GM machine.
Fixes Novell Bug #406123, thanks Christoph.
(cherry picked from commit f2ec3fd8f2c63b1bc0745802dcf737eda4bb42b6)
(cherry picked from commit 92ec2fc750ce17b1ec36493e8d731ef4b0bb772d)
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index e81b27c..5eb01be 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -286,6 +286,8 @@ static i830_quirk i830_quirk_list[] = {
{ PCI_CHIP_I915_GM, 0x1179, 0x0001, quirk_pipea_force },
/* Intel 855GM hardware (See LP: #216490) */
{ PCI_CHIP_I855_GM, 0x1028, 0x00c8, quirk_pipea_force },
+ /* Intel 855GM hardware (See Novell Bugzilla #406123) */
+ { PCI_CHIP_I855_GM, 0x10cf, 0x1215, quirk_pipea_force },
/* ThinkPad X40 needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1014, 0x0557, quirk_pipea_force },
commit 33a91f69e6a46d82537d93dd88508805914fcf47
Author: Zhenyu Wang <zhenyu.z.wang@intel.com>
Date: Thu Jul 3 01:03:14 2008 +0800
Fix official name for GM45 chipset
(cherry picked from commit a34a4e3f6420e2b06bbdaa124fe0ccb1bc6a0bd9)
diff --git a/src/common.h b/src/common.h
index 5efdc0c..201eac2 100644
--- a/src/common.h
+++ b/src/common.h
@@ -303,9 +303,9 @@ extern int I810_DEBUG;
#define PCI_CHIP_Q33_G_BRIDGE 0x29D0
#endif
-#ifndef PCI_CHIP_IGD_GM
-#define PCI_CHIP_IGD_GM 0x2A42
-#define PCI_CHIP_IGD_GM_BRIDGE 0x2A40
+#ifndef PCI_CHIP_GM45_GM
+#define PCI_CHIP_GM45_GM 0x2A42
+#define PCI_CHIP_GM45_BRIDGE 0x2A40
#endif
#ifndef PCI_CHIP_IGD_E_G
@@ -354,24 +354,24 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
-#define IS_IGD_GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
+#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_IGD_GM(pI810) || IS_G4X(pI810))
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_GM45(pI810) || IS_G4X(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */
-#define OVERLAY_NOEXIST(pI810) (IS_IGD_GM(pI810) || IS_G4X(pI810))
+#define OVERLAY_NOEXIST(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
/* chipsets require graphics mem for hardware status page */
-#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_IGD_GM(pI810) || IS_G4X(pI810))
+#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_GM45(pI810) || IS_G4X(pI810))
/* chipsets require status page in non stolen memory */
-#define HWS_NEED_NONSTOLEN(pI810) (IS_IGD_GM(pI810) || IS_G4X(pI810))
+#define HWS_NEED_NONSTOLEN(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index de4f3cb..8540646 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -152,7 +152,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
@@ -208,7 +208,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
- {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_GM45_GM, "Mobile Intel® GM45 Express Chipset"},
{PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"},
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
@@ -241,7 +241,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
- {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, RES_SHARED_VGA},
{PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA},
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
@@ -808,7 +808,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
- case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_GM45_GM:
case PCI_CHIP_IGD_E_G:
case PCI_CHIP_G45_G:
case PCI_CHIP_Q45_G:
diff --git a/src/i830_display.c b/src/i830_display.c
index a99ef3c..ba6de3a 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -667,7 +667,7 @@ i830_enable_fb_compression(xf86CrtcPtr crtc)
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_IGD_GM(pI830))
+ if (IS_GM45(pI830))
return i830_enable_fb_compression2(crtc);
i830_enable_fb_compression_8xx(crtc);
@@ -679,7 +679,7 @@ i830_disable_fb_compression(xf86CrtcPtr crtc)
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_IGD_GM(pI830))
+ if (IS_GM45(pI830))
return i830_disable_fb_compression2(crtc);
i830_disable_fb_compression_8xx(crtc);
@@ -1170,7 +1170,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
- if (IS_I965G(pI830) && !IS_IGD_GM(pI830))
+ if (IS_I965G(pI830) && !IS_GM45(pI830))
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
} else {
if (is_lvds) {
diff --git a/src/i830_driver.c b/src/i830_driver.c
index b1ab42a..6ad7089 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -251,7 +251,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_G33_G, "G33"},
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
- {PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_GM45_GM, "Mobile Intel® GM45 Express Chipset"},
{PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"},
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
@@ -278,7 +278,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA},
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
- {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, RES_SHARED_VGA},
{PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA},
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
@@ -653,7 +653,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- if (IS_IGD_GM(pI830) || IS_G4X(pI830)) {
+ if (IS_GM45(pI830) || IS_G4X(pI830)) {
gttaddr = pI830->MMIOAddr + MB(2);
pI830->GTTMapSize = MB(2);
} else {
@@ -962,7 +962,7 @@ i830_init_clock_gating(ScrnInfoPtr pScrn)
/* Disable clock gating reported to work incorrectly according to the specs.
*/
- if (IS_IGD_GM(pI830)) {
+ if (IS_GM45(pI830)) {
OUTREG(RENCLK_GATE_D1, 0);
OUTREG(RENCLK_GATE_D2, 0);
OUTREG(RAMCLK_GATE_D, 0);
@@ -1207,7 +1207,9 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
case PCI_CHIP_Q33_G:
chipname = "Q33";
break;
- case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_GM45_GM:
+ chipname = "Mobile Intel® GM45 Express Chipset";
+ break;
case PCI_CHIP_IGD_E_G:
chipname = "Intel Integrated Graphics Device";
break;
@@ -2102,7 +2104,7 @@ SaveHWState(ScrnInfoPtr pScrn)
pI830->saveRAMCLK_GATE_D = INREG(RAMCLK_GATE_D);
}
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
pI830->savePWRCTXA = INREG(PWRCTXA);
if (IS_MOBILE(pI830) && !IS_I830(pI830))
@@ -2170,7 +2172,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(RAMCLK_GATE_D, pI830->saveRAMCLK_GATE_D);
}
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
OUTREG(PWRCTXA, pI830->savePWRCTXA);
/*
@@ -2560,7 +2562,7 @@ i830_try_memory_allocation(ScrnInfoPtr pScrn)
if (!i830_allocate_2d_memory(pScrn))
goto failed;
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
if (!i830_allocate_pwrctx(pScrn))
goto failed;
@@ -2823,7 +2825,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
/* Enable FB compression if possible */
if (i830_fb_compression_supported(pI830) && !IS_I965GM(pI830)
- && !IS_IGD_GM(pI830))
+ && !IS_GM45(pI830))
pI830->fb_compression = TRUE;
else
pI830->fb_compression = FALSE;
@@ -2974,7 +2976,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* alone in that case.
* Also make sure the DRM can handle the swap.
*/
- if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_IGD_GM(pI830) &&
+ if (I830LVDSPresent(pScrn) && !IS_I965GM(pI830) && !IS_GM45(pI830) &&
(!pI830->directRenderingEnabled ||
(pI830->directRenderingEnabled && pI830->drmMinor >= 10))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "adjusting plane->pipe mappings "
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index b5e0c45..d1bbb3a 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -134,7 +134,7 @@ i830_set_lvds_backlight_method(xf86OutputPtr output)
if (i830_kernel_backlight_available(output)) {
method = BCM_KERNEL;
- } else if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
+ } else if (IS_I965GM(pI830) || IS_GM45(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
method = BCM_COMBO;
@@ -182,7 +182,7 @@ i830_lvds_get_backlight_max_native(xf86OutputPtr output)
uint32_t pwm_ctl = INREG(BLC_PWM_CTL);
int val;
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830)) {
+ if (IS_I965GM(pI830) || IS_GM45(pI830)) {
val = ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK2) >>
BACKLIGHT_MODULATION_FREQ_SHIFT2);
} else {
@@ -453,7 +453,7 @@ i830_lvds_save (xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
pI830->saveBLC_PWM_CTL2 = INREG(BLC_PWM_CTL2);
pI830->savePP_ON = INREG(LVDSPP_ON);
pI830->savePP_OFF = INREG(LVDSPP_OFF);
@@ -470,7 +470,7 @@ i830_lvds_restore(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
- if (IS_I965GM(pI830) || IS_IGD_GM(pI830))
+ if (IS_I965GM(pI830) || IS_GM45(pI830))
OUTREG(BLC_PWM_CTL2, pI830->saveBLC_PWM_CTL2);
OUTREG(BLC_PWM_CTL, pI830->saveBLC_PWM_CTL);
OUTREG(LVDSPP_ON, pI830->savePP_ON);
diff --git a/src/i830_memory.c b/src/i830_memory.c
index dcb2aa6..a8c5c92 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1282,7 +1282,7 @@ static void i830_setup_fb_compression(ScrnInfoPtr pScrn)
goto out;
}
- if (IS_IGD_GM(pI830)) {
+ if (IS_GM45(pI830)) {
/* Update i830_display.c too if compression ratio changes */
compressed_size = fb_height * (pScrn->displayWidth / 4);
} else {
@@ -1309,7 +1309,7 @@ static void i830_setup_fb_compression(ScrnInfoPtr pScrn)
goto out;
}
- if (!IS_IGD_GM(pI830)) {
+ if (!IS_GM45(pI830)) {
pI830->compressed_ll_buffer =
i830_allocate_memory(pScrn, "compressed ll buffer",
FBC_LL_SIZE + FBC_LL_PAD, KB(4),
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index f7659f0..e81b27c 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -266,9 +266,9 @@ static i830_quirk i830_quirk_list[] = {
{ PCI_CHIP_I965_GM, 0x144d, 0xc510, quirk_ignore_tv },
/* HP Compaq 6730s has no TV output */
- { PCI_CHIP_IGD_GM, 0x103c, 0x30e8, quirk_ignore_tv },
+ { PCI_CHIP_GM45_GM, 0x103c, 0x30e8, quirk_ignore_tv },
/* HP Pavilion ze4944ea needs pipe A force quirk (See LP: #242389) */
- { PCI_CHIP_IGD_GM, 0x103c, 0x3084, quirk_pipea_force },
+ { PCI_CHIP_GM45_GM, 0x103c, 0x3084, quirk_pipea_force },
/* Thinkpad R31 needs pipe A force quirk */
{ PCI_CHIP_I830_M, 0x1014, 0x0505, quirk_pipea_force },
diff --git a/src/i965_render.c b/src/i965_render.c
index 9afa327..3273d0d 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -983,7 +983,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_IGD_GM(pI830) || IS_G4X(pI830))
+ if (IS_GM45(pI830) || IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
diff --git a/src/i965_video.c b/src/i965_video.c
index bee858e..5d978ba 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -509,7 +509,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_IGD_GM(pI830) || IS_G4X(pI830))
+ if (IS_GM45(pI830) || IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
commit bd2203a3a2ece7f70aae42a811421bb04ec33bc6
Author: Julien Cristau <jcristau@debian.org>
Date: Sun Jul 27 01:35:04 2008 +0200
The phase shift its are now reserved.
(cherry picked from commit 9a05662918223477eb1cf6f80ffac08712721c70)
(cherry picked from commit 82300116af8b01fc3c071d9c8625ffea122431fa)
Conflicts:
src/i830_hdmi.c
diff --git a/src/i830_display.c b/src/i830_display.c
index df2f1a2..a99ef3c 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1170,7 +1170,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
- if (IS_I965G(pI830))
+ if (IS_I965G(pI830) && !IS_IGD_GM(pI830))
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
} else {
if (is_lvds) {
commit c2e2384bf145c138a45a90a74e7c4269d931797b
Author: Zhenyu Wang <zhenyu.z.wang@intel.com>
Date: Wed Jul 2 11:12:54 2008 +0800
Give asus and eeepc backlight method higher priority
On #16418, Evgeniy Manachkin <sfstudio@mail.ru> reported that
last asus and eeepc backlight patch is wrong, as acpi_video0 method
will take priority and doesn't work.
(cherry picked from commit 6506ac7aa008436158db4f4196802cab462f3446)
(cherry picked from commit cb4c1fa7499d82beb01566aaf1f323a03ebc1ae4)
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index 4f62a2b..b5e0c45 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -83,6 +83,8 @@ struct i830_lvds_priv {
* List of available kernel interfaces in priority order
*/
static char *backlight_interfaces[] = {
+ "asus-laptop",
+ "eeepc",
"thinkpad_screen",
"acpi_video1",
"acpi_video0",
commit 094fb03df0549d2016843c80289653f5243d7f0b
Author: Roland Test-tools Bär <roland@verifysoft.de>
Date: Mon Jun 30 10:32:42 2008 -0700
i810: Remove an effectively unused variable (only used in an incorrect free())
Bug #15401.
(cherry picked from commit 0597d94001afe0a9a34104285ce4dffc75b68071)
(cherry picked from commit 696f9783cc0e269ac8c5c65d8889f22524b5c5e4)
diff --git a/src/xvmc/I810XvMC.c b/src/xvmc/I810XvMC.c
index 03be251..ce5395a 100644
--- a/src/xvmc/I810XvMC.c
+++ b/src/xvmc/I810XvMC.c
@@ -130,7 +130,6 @@ Status XvMCCreateContext(Display *display, XvPortID port,
int surface_type_id, int width, int height, int flags,
XvMCContext *context) {
i810XvMCContext *pI810XvMC;
- char busIdString[10];
int priv_count;
uint *priv_data;
uint magic;
@@ -217,7 +216,6 @@ Status XvMCCreateContext(Display *display, XvPortID port,
/* Open DRI Device */
if((pI810XvMC->fd = drmOpen("i810",NULL)) < 0) {
printf("DRM Device for i810 could not be opened.\n");
- free(busIdString);
free(pI810XvMC);
return BadAccess;
} /* !pI810XvMC->fd */
commit 2cee63fd6db915fe2811cae6b7263656f7b933a2
Author: Jesse Barnes <jbarnes@jbarnes-t61.(none)>
Date: Fri Jun 27 13:39:31 2008 -0700
Add pipea force enable quirk for HP Pavilion ze4944ea
Fixes bug #16540, thanks Bryce.
(cherry picked from commit 0283d22f510ba47dfdac2806a58e46649c26580b)
(cherry picked from commit c61480f420445f7e3341305362b8cea656b0f7a2)
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 1beda4b..f7659f0 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -267,6 +267,8 @@ static i830_quirk i830_quirk_list[] = {
/* HP Compaq 6730s has no TV output */
{ PCI_CHIP_IGD_GM, 0x103c, 0x30e8, quirk_ignore_tv },
+ /* HP Pavilion ze4944ea needs pipe A force quirk (See LP: #242389) */
+ { PCI_CHIP_IGD_GM, 0x103c, 0x3084, quirk_pipea_force },
/* Thinkpad R31 needs pipe A force quirk */
{ PCI_CHIP_I830_M, 0x1014, 0x0505, quirk_pipea_force },
commit 3b655a38a7b10e8b3b1056715bd3fdf9528ab96c
Author: Jesse Barnes <jbarnes@jbarnes-t61.(none)>
Date: Fri Jun 27 13:37:10 2008 -0700
Add pipe a force enable quirk for Lenovo T60
Fixes bug #16494.
(cherry picked from commit 08903abe4dc0295c7ed7d1ff1a22e0e579540c15)
(cherry picked from commit 9869cd11549cd608593fea111880502192e93fd5)
diff --git a/src/i830_quirks.c b/src/i830_quirks.c
index 1bd8885..1beda4b 100644
--- a/src/i830_quirks.c
+++ b/src/i830_quirks.c
@@ -288,6 +288,9 @@ static i830_quirk i830_quirk_list[] = {
/* ThinkPad X40 needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1014, 0x0557, quirk_pipea_force },
+ /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
+ { PCI_CHIP_I945_GM, 0x17aa, 0x201a, quirk_pipea_force },
+
/* Sony vaio PCG-r600HFP (fix bug 13722) */
{ PCI_CHIP_I830_M, 0x104d, 0x8100, quirk_ivch_dvob },
/* Sony vaio VGN-SZ4MN (See LP: #212163) */
commit cf0c332f0c249d8f04aabd035c157ab3e9091734
Author: Zhenyu Wang <zhenyu.z.wang@intel.com>
Date: Tue Jun 17 12:39:28 2008 -0700
Add support for Intel 4 series chipsets.
(cherry picked from commit 1cfe769c74d1a3a392bf1aaaf5c2dcc8273daf66)
(cherry picked from commit 093f65fd04c38e6c1f19889074f9316749959c7a)
diff --git a/src/common.h b/src/common.h
index 9a3e0ac..5efdc0c 100644
--- a/src/common.h
+++ b/src/common.h
@@ -308,6 +308,21 @@ extern int I810_DEBUG;
#define PCI_CHIP_IGD_GM_BRIDGE 0x2A40
#endif
+#ifndef PCI_CHIP_IGD_E_G
+#define PCI_CHIP_IGD_E_G 0x2E02
+#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00
+#endif
+
+#ifndef PCI_CHIP_G45_G
+#define PCI_CHIP_G45_G 0x2E22
+#define PCI_CHIP_G45_G_BRIDGE 0x2E20
+#endif
+
+#ifndef PCI_CHIP_Q45_G
+#define PCI_CHIP_Q45_G 0x2E12
+#define PCI_CHIP_Q45_G_BRIDGE 0x2E10
+#endif
+
#if XSERVER_LIBPCIACCESS
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
@@ -340,8 +355,9 @@ extern int I810_DEBUG;
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
#define IS_IGD_GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
+#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G)
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_IGD_GM(pI810))
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_IGD_GM(pI810) || IS_G4X(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
@@ -350,8 +366,12 @@ extern int I810_DEBUG;
#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_IGD_GM(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
+/* mark chipsets without overlay hw */
+#define OVERLAY_NOEXIST(pI810) (IS_IGD_GM(pI810) || IS_G4X(pI810))
/* chipsets require graphics mem for hardware status page */
-#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_IGD_GM(pI810))
+#define HWS_NEED_GFX(pI810) (IS_G33CLASS(pI810) || IS_IGD_GM(pI810) || IS_G4X(pI810))
+/* chipsets require status page in non stolen memory */
+#define HWS_NEED_NONSTOLEN(pI810) (IS_IGD_GM(pI810) || IS_G4X(pI810))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 4b71660..de4f3cb 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -153,6 +153,9 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
{ 0, 0, 0 },
};
@@ -206,6 +209,9 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
{PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_G45_G, "G45/G43"},
+ {PCI_CHIP_Q45_G, "Q45/Q43"},
{-1, NULL}
};
@@ -236,6 +242,9 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
{PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA},
+ {PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
+ {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@@ -800,6 +809,9 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_IGD_E_G:
+ case PCI_CHIP_G45_G:
+ case PCI_CHIP_Q45_G:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 79a5b1e..cb47eaa 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -2236,6 +2236,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
+#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
+#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
+#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
+#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
+
#define I85X_CAPID 0x44
#define I85X_VARIANT_MASK 0x7
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 563d167..b1ab42a 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -252,6 +252,9 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
{PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_G45_G, "G45/G43"},
+ {PCI_CHIP_Q45_G, "Q45/Q43"},
{-1, NULL}
};
@@ -276,6 +279,9 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
{PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA},
+ {PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
+ {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@@ -511,6 +517,10 @@ I830DetectMemory(ScrnInfoPtr pScrn)
*/
range = gtt_size + 4;
+ /* new 4 series hardware has seperate GTT stolen with GFX stolen */
+ if (IS_G4X(pI830))
+ range = 0;
+
if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
case I855_GMCH_GMS_STOLEN_1M:
@@ -544,6 +554,22 @@ I830DetectMemory(ScrnInfoPtr pScrn)
if (IS_I9XX(pI830))
memsize = MB(256) - KB(range);
break;
+ case INTEL_GMCH_GMS_STOLEN_96M:
+ if (IS_I9XX(pI830))
+ memsize = MB(96) - KB(range);
+ break;
+ case INTEL_GMCH_GMS_STOLEN_160M:
+ if (IS_I9XX(pI830))
+ memsize = MB(160) - KB(range);
+ break;
+ case INTEL_GMCH_GMS_STOLEN_224M:
+ if (IS_I9XX(pI830))
+ memsize = MB(224) - KB(range);
+ break;
+ case INTEL_GMCH_GMS_STOLEN_352M:
+ if (IS_I9XX(pI830))
+ memsize = MB(352) - KB(range);
+ break;
}
} else {
switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
@@ -627,7 +653,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- if (IS_IGD_GM(pI830)) {
+ if (IS_IGD_GM(pI830) || IS_G4X(pI830)) {
gttaddr = pI830->MMIOAddr + MB(2);
pI830->GTTMapSize = MB(2);
} else {
@@ -1182,8 +1208,15 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
chipname = "Q33";
break;
case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_IGD_E_G:
chipname = "Intel Integrated Graphics Device";
break;
+ case PCI_CHIP_G45_G:
+ chipname = "G45/G43";
+ break;
+ case PCI_CHIP_Q45_G:
+ chipname = "Q45/Q43";
+ break;
default:
chipname = "unknown chipset";
break;
@@ -2901,7 +2934,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
"needs 2D acceleration.\n");
pI830->XvEnabled = FALSE;
}
- if (!IS_IGD_GM(pI830) && pI830->overlay_regs == NULL) {
+ if (!OVERLAY_NOEXIST(pI830) && pI830->overlay_regs == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Disabling Xv because the overlay register buffer "
"allocation failed.\n");
diff --git a/src/i830_memory.c b/src/i830_memory.c
index ccbe7bd..dcb2aa6 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -447,7 +447,7 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
/* Overlay and cursors, if physical, need to be allocated outside
* of the kernel memory manager.
*/
- if (!OVERLAY_NOPHYSICAL(pI830) && !IS_IGD_GM(pI830)) {
+ if (!OVERLAY_NOPHYSICAL(pI830) && !OVERLAY_NOEXIST(pI830)) {
mmsize -= ROUND_TO(OVERLAY_SIZE, GTT_PAGE_SIZE);
}
if (pI830->CursorNeedsPhysical) {
@@ -459,7 +459,8 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
/* Can't do TTM on stolen memory */
mmsize -= pI830->stolen_size;
- if (HWS_NEED_GFX(pI830) && IS_IGD_GM(pI830))
+ /* new chipsets need non-stolen status page */
+ if (HWS_NEED_GFX(pI830) && HWS_NEED_NONSTOLEN(pI830))
mmsize -= HWSTATUS_PAGE_SIZE;
/* Create the aperture allocation */
@@ -1027,7 +1028,7 @@ i830_allocate_overlay(ScrnInfoPtr pScrn)
if (!pI830->XvEnabled)
return TRUE;
- if (IS_IGD_GM(pI830))
+ if (OVERLAY_NOEXIST(pI830))
return TRUE;
if (!OVERLAY_NOPHYSICAL(pI830))
@@ -1643,7 +1644,7 @@ i830_allocate_hwstatus(ScrnInfoPtr pScrn)
* (i.e. not through buffer objects).
*/
flags = NEED_LIFETIME_FIXED;
- if (IS_IGD_GM(pI830))
+ if (HWS_NEED_NONSTOLEN(pI830))
flags |= NEED_NON_STOLEN;
pI830->hw_status = i830_allocate_memory(pScrn, "HW status",
HWSTATUS_PAGE_SIZE, GTT_PAGE_SIZE, flags);
diff --git a/src/i830_video.c b/src/i830_video.c
index 91e0e00..8bbc7ff 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -620,7 +620,7 @@ I830InitVideo(ScreenPtr pScreen)
}
/* Set up overlay video if we can do it at this depth. */
- if (!IS_IGD_GM(pI830) && pScrn->bitsPerPixel != 8 &&
+ if (!OVERLAY_NOEXIST(pI830) && pScrn->bitsPerPixel != 8 &&
pI830->overlay_regs != NULL)
{
overlayAdaptor = I830SetupImageVideoOverlay(pScreen);
diff --git a/src/i965_render.c b/src/i965_render.c
index 96082bb..9afa327 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -983,7 +983,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_IGD_GM(pI830))
+ if (IS_IGD_GM(pI830) || IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
diff --git a/src/i965_video.c b/src/i965_video.c
index 153a967..bee858e 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -509,7 +509,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_IGD_GM(pI830))
+ if (IS_IGD_GM(pI830) || IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
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