mesa: Changes to 'upstream-experimental'
configure.ac | 2
include/pci_ids/radeonsi_pci_ids.h | 14 +
scons/gallium.py | 2
src/gallium/drivers/r300/r300_state.c | 11 +
src/gallium/drivers/r300/r300_texture.c | 6
src/gallium/drivers/r600/evergreen_state.c | 4
src/gallium/drivers/r600/r600_hw_context.c | 12 +
src/gallium/drivers/r600/r600_pipe.h | 28 +++
src/gallium/drivers/r600/r600_state.c | 3
src/gallium/drivers/r600/r600_state_common.c | 13 +
src/gallium/drivers/r600/r600_texture.c | 1
src/gallium/drivers/radeon/radeon_llvm.h | 2
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 50 +++---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 3
src/gallium/drivers/radeonsi/radeonsi_shader.c | 150 ++++++++++++++------
src/gallium/drivers/radeonsi/si_state.c | 10 -
src/gallium/drivers/radeonsi/si_state_draw.c | 7
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 11 +
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1
src/gallium/winsys/radeon/drm/radeon_winsys.h | 11 +
src/mesa/main/extensions.c | 2
21 files changed, 262 insertions(+), 81 deletions(-)
New commits:
commit f1c46c84189e548331e94f296530f98b5b002f10
Author: Marek Olšák <maraeo@gmail.com>
Date: Fri Feb 1 20:59:38 2013 +0100
r300g: fix blending with blend color and RGBA formats
NOTE: This is a candidate for the stable branches.
(cherry picked from commit f40a7fc34a601195191b1b2ffef55818a4086d5f)
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index fd02f82..377b726 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -487,6 +487,7 @@ static void r300_set_blend_color(struct pipe_context* pipe,
(struct r300_blend_color_state*)r300->blend_color_state.state;
struct pipe_blend_color c;
enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0;
+ float tmp;
CB_LOCALS;
state->state = *color; /* Save it, so that we can reuse it in set_fb_state */
@@ -513,6 +514,13 @@ static void r300_set_blend_color(struct pipe_context* pipe,
c.color[2] = c.color[3];
break;
+ case PIPE_FORMAT_R8G8B8A8_UNORM:
+ case PIPE_FORMAT_R8G8B8X8_UNORM:
+ tmp = c.color[0];
+ c.color[0] = c.color[2];
+ c.color[2] = tmp;
+ break;
+
default:;
}
}
@@ -919,6 +927,9 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
/* Need to reset clamping or colormask. */
r300_mark_atom_dirty(r300, &r300->blend_state);
+ /* Re-swizzle the blend color. */
+ r300_set_blend_color(pipe, &((struct r300_blend_color_state*)r300->blend_color_state.state)->state);
+
/* If zsbuf is set from NULL to non-NULL or vice versa.. */
if (!!old_state->zsbuf != !!state->zsbuf) {
r300_mark_atom_dirty(r300, &r300->dsa_state);
commit 4bc85f9aac46d2442eb6194bd15c5995b281071f
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Tue Feb 5 15:12:14 2013 +0100
Require libdrm_radeon 2.4.42 for radeonsi.
It has new PCI IDs and an important tiled surface layout fix.
(cherry picked from commit 02a423b23936a0757f5171535235707c5444b9bc)
diff --git a/configure.ac b/configure.ac
index 564ca3c..ef6da49 100644
--- a/configure.ac
+++ b/configure.ac
@@ -30,7 +30,7 @@ AC_SUBST([OSMESA_VERSION])
dnl Versions for external dependencies
LIBDRM_REQUIRED=2.4.24
-LIBDRM_RADEON_REQUIRED=2.4.40
+LIBDRM_RADEON_REQUIRED=2.4.42
LIBDRM_INTEL_REQUIRED=2.4.38
LIBDRM_NVVIEUX_REQUIRED=2.4.33
LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41"
diff --git a/scons/gallium.py b/scons/gallium.py
index a8b1f03..4b51b6e 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -530,7 +530,7 @@ def generate(env):
env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
env.PkgCheckModules('DRM', ['libdrm >= 2.4.24'])
env.PkgCheckModules('DRM_INTEL', ['libdrm_intel >= 2.4.30'])
- env.PkgCheckModules('DRM_RADEON', ['libdrm_radeon >= 2.4.40'])
+ env.PkgCheckModules('DRM_RADEON', ['libdrm_radeon >= 2.4.42'])
env.PkgCheckModules('XORG', ['xorg-server >= 1.6.0'])
env.PkgCheckModules('KMS', ['libkms >= 2.4.24'])
env.PkgCheckModules('UDEV', ['libudev > 150'])
commit e1d798a9015d330f23aef5ad2ca10c5844e704e7
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Thu Jan 24 19:11:28 2013 -0500
radeonsi: add Oland pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Note: this is a candidate for the 9.1 branch.
(cherry picked from commit 4161d70bba567e6e73d5e9e993a74d81930d0e72)
diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h
index a885a44..22c96c0 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -46,3 +46,17 @@ CHIPSET(0x6839, VERDE_6839, VERDE)
CHIPSET(0x683B, VERDE_683B, VERDE)
CHIPSET(0x683D, VERDE_683D, VERDE)
CHIPSET(0x683F, VERDE_683F, VERDE)
+
+CHIPSET(0x6600, OLAND_6600, OLAND)
+CHIPSET(0x6601, OLAND_6601, OLAND)
+CHIPSET(0x6602, OLAND_6602, OLAND)
+CHIPSET(0x6603, OLAND_6603, OLAND)
+CHIPSET(0x6606, OLAND_6606, OLAND)
+CHIPSET(0x6607, OLAND_6607, OLAND)
+CHIPSET(0x6610, OLAND_6610, OLAND)
+CHIPSET(0x6611, OLAND_6611, OLAND)
+CHIPSET(0x6613, OLAND_6613, OLAND)
+CHIPSET(0x6620, OLAND_6620, OLAND)
+CHIPSET(0x6621, OLAND_6621, OLAND)
+CHIPSET(0x6623, OLAND_6623, OLAND)
+CHIPSET(0x6631, OLAND_6631, OLAND)
commit 6b0fa537a99bb961d47069da952900edb4f4613d
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Thu Jan 24 19:09:48 2013 -0500
radeonsi: default PA_SC_RASTER_CONFIG to 0
That should work in all cases.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Note: this is a candidate for the 9.1 branch.
(cherry picked from commit af0af75881ea99452086afd6907780de77af6e96)
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 6478e9a..6e50832 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2662,12 +2662,14 @@ void si_init_config(struct r600_context *rctx)
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
break;
case CHIP_VERDE:
- default:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
break;
case CHIP_OLAND:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
break;
+ default:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+ break;
}
si_pm4_set_state(rctx, init, pm4);
commit 0cc0097bb03e1790c4598016343fa91cfd39e10c
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Thu Jan 24 19:08:07 2013 -0500
radeonsi: add support for Oland chips
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Note: this is a candidate for the 9.1 branch
(cherry picked from commit 83e4407f443fb6baeccf9aefee291c82adcaa58b)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 9ec3fe3..9a71bcc 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -280,6 +280,7 @@ static const char *r600_get_family_name(enum radeon_family family)
case CHIP_TAHITI: return "AMD TAHITI";
case CHIP_PITCAIRN: return "AMD PITCAIRN";
case CHIP_VERDE: return "AMD CAPE VERDE";
+ case CHIP_OLAND: return "AMD OLAND";
default: return "AMD unknown";
}
}
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index e81079e..6478e9a 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2665,6 +2665,9 @@ void si_init_config(struct r600_context *rctx)
default:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
break;
+ case CHIP_OLAND:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
+ break;
}
si_pm4_set_state(rctx, init, pm4);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index d23220d..62ba4b1 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -312,6 +312,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
+ case CHIP_OLAND:
ws->info.chip_class = TAHITI;
break;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 8b64ef2..c57a87d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -123,6 +123,7 @@ enum radeon_family {
CHIP_TAHITI,
CHIP_PITCAIRN,
CHIP_VERDE,
+ CHIP_OLAND,
CHIP_LAST,
};
commit 7f90de54142647966169165079a952ce648ddb06
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Fri Feb 1 18:49:07 2013 +0100
radeonsi: Fix draws using user index buffer.
Was broken since commit bf469f4edc60bd1c5fd770cb231b8d5ab801427f
('gallium: add void *user_buffer in pipe_index_buffer').
Fixes 11 piglit tests and lots of missing geometry e.g. in TORCS.
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit a8a5055f2dea1960898763d17f28043577c3e64e)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index ef94eae..3704410 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -524,10 +524,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
struct pipe_index_buffer ib = {};
uint32_t cp_coher_cntl;
- if ((!info->count && (info->indexed || !info->count_from_stream_output)) ||
- (info->indexed && !rctx->index_buffer.buffer)) {
+ if (!info->count && (info->indexed || !info->count_from_stream_output))
return;
- }
if (!rctx->ps_shader || !rctx->vs_shader)
return;
@@ -538,13 +536,14 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
if (info->indexed) {
/* Initialize the index buffer struct. */
pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
+ ib.user_buffer = rctx->index_buffer.user_buffer;
ib.index_size = rctx->index_buffer.index_size;
ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
/* Translate or upload, if needed. */
r600_translate_index_buffer(rctx, &ib, info->count);
- if (ib.user_buffer) {
+ if (ib.user_buffer && !ib.buffer) {
r600_upload_index_buffer(rctx, &ib, info->count);
}
commit 8cd237bcbe415475d70526039c12ab6a36082365
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Fri Jan 25 16:04:37 2013 +0100
radeonsi: Remove spurious traces of R16G16B16 support.
The hardware can't do it, and these were causing warnings in some piglit tests.
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit 6455d40b7ec09e3a3923c9b78952dc29627afed1)
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index aba44df..e81079e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -804,15 +804,12 @@ static uint32_t si_translate_colorformat(enum pipe_format format)
return V_028C70_COLOR_10_11_11;
/* 64-bit buffers. */
- case PIPE_FORMAT_R16G16B16_USCALED:
- case PIPE_FORMAT_R16G16B16_SSCALED:
case PIPE_FORMAT_R16G16B16A16_UINT:
case PIPE_FORMAT_R16G16B16A16_SINT:
case PIPE_FORMAT_R16G16B16A16_USCALED:
case PIPE_FORMAT_R16G16B16A16_SSCALED:
case PIPE_FORMAT_R16G16B16A16_UNORM:
case PIPE_FORMAT_R16G16B16A16_SNORM:
- case PIPE_FORMAT_R16G16B16_FLOAT:
case PIPE_FORMAT_R16G16B16A16_FLOAT:
return V_028C70_COLOR_16_16_16_16;
commit 5ca77c27a6ded205d28204076e165d2f2e5afc93
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Fri Jan 25 18:30:30 2013 +0100
radeonsi: Enable texture arrays.
28/30 piglit tests pass.
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit 6bcb8238446060db665425d9f63eb0c1b3ba9f68)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 471dd48..9ec3fe3 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -379,7 +379,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 15;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return /*rscreen->info.drm_minor >= 9 ? 16384 :*/ 0;
+ return 16384;
case PIPE_CAP_MAX_COMBINED_SAMPLERS:
return 32;
commit b104d151f19afbc34f9d13c5dd84ac8198c11331
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Fri Jan 25 12:10:11 2013 +0100
radeonsi: Improve packing of texture address parameters.
In particular, the LOD bias and depth comparison values are packed before the
'normal' texture coordinates, and the array slice and LOD values are appended.
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit 120efeef8b51c16924dafa6bbeb017a856db911b)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 575cc67..e639566 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -793,59 +793,127 @@ static void tex_fetch_args(
{
struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_instruction * inst = emit_data->inst;
+ unsigned opcode = inst->Instruction.Opcode;
+ unsigned target = inst->Texture.Texture;
LLVMValueRef ptr;
LLVMValueRef offset;
- LLVMValueRef coords[5];
+ LLVMValueRef coords[4];
+ LLVMValueRef address[16];
+ unsigned count = 0;
unsigned chan;
/* WriteMask */
/* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, 0xf);
- /* Coordinates */
- /* XXX: Not all sample instructions need 4 address arguments. */
- if (inst->Instruction.Opcode == TGSI_OPCODE_TXP)
- coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W)
-;
-
+ /* Fetch and project texture coordinates */
+ coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
for (chan = 0; chan < 3; chan++ ) {
coords[chan] = lp_build_emit_fetch(bld_base,
emit_data->inst, 0,
chan);
- if (inst->Instruction.Opcode == TGSI_OPCODE_TXP)
+ if (opcode == TGSI_OPCODE_TXP)
coords[chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_DIV,
coords[chan],
coords[3]);
}
- coords[3] = bld_base->base.one;
+ if (opcode == TGSI_OPCODE_TXP)
+ coords[3] = bld_base->base.one;
- if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
- inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
- inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
- /* These instructions have additional operand that should be packed
- * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords.
- * That operand should be passed as a float value in the args array
- * right after the coord vector. After packing it's not used anymore,
- * that's why arg_count is not increased */
- coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
- }
+ /* Pack LOD bias value */
+ if (opcode == TGSI_OPCODE_TXB)
+ address[count++] = coords[3];
- if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
- inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
- inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
+ if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
+ opcode != TGSI_OPCODE_TXQ)
radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
+
+ /* Pack depth comparison value */
+ switch (target) {
+ case TGSI_TEXTURE_SHADOW1D:
+ case TGSI_TEXTURE_SHADOW1D_ARRAY:
+ case TGSI_TEXTURE_SHADOW2D:
+ case TGSI_TEXTURE_SHADOWRECT:
+ address[count++] = coords[2];
+ break;
+ case TGSI_TEXTURE_SHADOWCUBE:
+ case TGSI_TEXTURE_SHADOW2D_ARRAY:
+ address[count++] = coords[3];
+ break;
+ case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
+ address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
}
- for (chan = 0; chan < 4; chan++ ) {
- coords[chan] = LLVMBuildBitCast(gallivm->builder,
- coords[chan],
- LLVMInt32TypeInContext(gallivm->context),
- "");
+ /* Pack texture coordinates */
+ address[count++] = coords[0];
+ switch (target) {
+ case TGSI_TEXTURE_2D:
+ case TGSI_TEXTURE_2D_ARRAY:
+ case TGSI_TEXTURE_3D:
+ case TGSI_TEXTURE_CUBE:
+ case TGSI_TEXTURE_RECT:
+ case TGSI_TEXTURE_SHADOW2D:
+ case TGSI_TEXTURE_SHADOWRECT:
+ case TGSI_TEXTURE_SHADOW2D_ARRAY:
+ case TGSI_TEXTURE_SHADOWCUBE:
+ case TGSI_TEXTURE_2D_MSAA:
+ case TGSI_TEXTURE_2D_ARRAY_MSAA:
+ case TGSI_TEXTURE_CUBE_ARRAY:
+ case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
+ address[count++] = coords[1];
+ }
+ switch (target) {
+ case TGSI_TEXTURE_3D:
+ case TGSI_TEXTURE_CUBE:
+ case TGSI_TEXTURE_SHADOWCUBE:
+ case TGSI_TEXTURE_CUBE_ARRAY:
+ case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
+ address[count++] = coords[2];
+ }
+
+ /* Pack array slice */
+ switch (target) {
+ case TGSI_TEXTURE_1D_ARRAY:
+ address[count++] = coords[1];
}
+ switch (target) {
+ case TGSI_TEXTURE_2D_ARRAY:
+ case TGSI_TEXTURE_2D_ARRAY_MSAA:
+ case TGSI_TEXTURE_SHADOW2D_ARRAY:
+ address[count++] = coords[2];
+ }
+ switch (target) {
+ case TGSI_TEXTURE_CUBE_ARRAY:
+ case TGSI_TEXTURE_SHADOW1D_ARRAY:
+ case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
+ address[count++] = coords[3];
+ }
+
+ /* Pack LOD */
+ if (opcode == TGSI_OPCODE_TXL)
+ address[count++] = coords[3];
+
+ if (count > 16) {
+ assert(!"Cannot handle more than 16 texture address parameters");
+ count = 16;
+ }
+
+ for (chan = 0; chan < count; chan++ ) {
+ address[chan] = LLVMBuildBitCast(gallivm->builder,
+ address[chan],
+ LLVMInt32TypeInContext(gallivm->context),
+ "");
+ }
+
+ /* Pad to power of two vector */
+ while (count < util_next_power_of_two(count))
+ address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
- emit_data->args[1] = lp_build_gather_values(gallivm, coords, 4);
+ emit_data->dst_type = LLVMVectorType(LLVMInt32TypeInContext(gallivm->context),
+ count);
+ emit_data->args[1] = lp_build_gather_values(gallivm, address, count);
/* Resource */
ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V8I32, SI_SGPR_RESOURCE);
@@ -862,8 +930,7 @@ static void tex_fetch_args(
ptr, offset);
/* Dimensions */
- emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm,
- emit_data->inst->Texture.Texture);
+ emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm, target);
emit_data->arg_count = 5;
/* XXX: To optimize, we could use a float or v2f32, if the last bits of
commit 5f9f3f381f7616fb07b63fece4480e0db43cec3c
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Thu Jan 24 18:54:51 2013 +0100
radeonsi: Adapt to sample intrinsics changes.
Fix up intrinsic names, and bitcast texture address parameters to integers.
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit e5fb7347a72118bf06dfabaa453208578c7ad876)
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h b/src/gallium/drivers/radeon/radeon_llvm.h
index 64d838a..21360e2 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -155,7 +155,7 @@ static inline LLVMValueRef bitcast(
void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data,
- unsigned coord_arg);
+ LLVMValueRef *coords_arg);
void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index c645326..0f90991 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -531,7 +531,7 @@ static void kil_emit(
void radeon_llvm_emit_prepare_cube_coords(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data,
- unsigned coord_arg)
+ LLVMValueRef *coords_arg)
{
unsigned target = emit_data->inst->Texture.Texture;
@@ -542,11 +542,13 @@ void radeon_llvm_emit_prepare_cube_coords(
LLVMValueRef coords[4];
LLVMValueRef mad_args[3];
LLVMValueRef idx;
+ struct LLVMOpaqueValue *cube_vec;
+ LLVMValueRef v;
unsigned i;
- LLVMValueRef v = build_intrinsic(builder, "llvm.AMDGPU.cube",
- LLVMVectorType(type, 4),
- &emit_data->args[coord_arg], 1, LLVMReadNoneAttribute);
+ cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
+ v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
+ &cube_vec, 1, LLVMReadNoneAttribute);
for (i = 0; i < 4; ++i) {
idx = lp_build_const_int32(gallivm, i);
@@ -579,18 +581,14 @@ void radeon_llvm_emit_prepare_cube_coords(
if (target != TGSI_TEXTURE_CUBE ||
opcode != TGSI_OPCODE_TEX) {
- /* load source coord.w component - array_index for cube arrays or
- * compare value for SHADOWCUBE */
- idx = lp_build_const_int32(gallivm, 3);
- coords[3] = LLVMBuildExtractElement(builder,
- emit_data->args[coord_arg], idx, "");
-
/* for cube arrays coord.z = coord.w(array_index) * 8 + face */
if (target == TGSI_TEXTURE_CUBE_ARRAY ||
target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
+ /* coords_arg.w component - array_index for cube arrays or
+ * compare value for SHADOWCUBE */
coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
- coords[3], lp_build_const_float(gallivm, 8.0), coords[2]);
+ coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
}
/* for instructions that need additional src (compare/lod/bias),
@@ -598,12 +596,11 @@ void radeon_llvm_emit_prepare_cube_coords(
if (opcode == TGSI_OPCODE_TEX2 ||
opcode == TGSI_OPCODE_TXB2 ||
opcode == TGSI_OPCODE_TXL2) {
- coords[3] = emit_data->args[coord_arg + 1];
+ coords[3] = coords_arg[4];
}
}
- emit_data->args[coord_arg] =
- lp_build_gather_values(bld_base->base.gallivm, coords, 4);
+ memcpy(coords_arg, coords, sizeof(coords));
}
static void txd_fetch_args(
@@ -645,9 +642,6 @@ static void txp_fetch_args(
TGSI_OPCODE_DIV, arg, src_w);
}
coords[3] = bld_base->base.one;
- emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
- coords, 4);
- emit_data->arg_count = 1;
if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
@@ -655,8 +649,12 @@ static void txp_fetch_args(
inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
- radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, 0);
+ radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
}
+
+ emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
+ coords, 4);
+ emit_data->arg_count = 1;
}
static void tex_fetch_args(
@@ -673,17 +671,12 @@ static void tex_fetch_args(
const struct tgsi_full_instruction * inst = emit_data->inst;
- LLVMValueRef coords[4];
+ LLVMValueRef coords[5];
unsigned chan;
for (chan = 0; chan < 4; chan++) {
coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
}
- emit_data->arg_count = 1;
- emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
- coords, 4);
- emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
-
if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
@@ -692,7 +685,7 @@ static void tex_fetch_args(
* That operand should be passed as a float value in the args array
* right after the coord vector. After packing it's not used anymore,
* that's why arg_count is not increased */
- emit_data->args[1] = lp_build_emit_fetch(bld_base, inst, 1, 0);
+ coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
}
if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
@@ -701,8 +694,13 @@ static void tex_fetch_args(
inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
- radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, 0);
+ radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
}
+
+ emit_data->arg_count = 1;
+ emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
+ coords, 4);
+ emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
}
static void txf_fetch_args(
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index f398e6c..575cc67 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -791,9 +791,12 @@ static void tex_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
+ struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_instruction * inst = emit_data->inst;
LLVMValueRef ptr;
LLVMValueRef offset;
+ LLVMValueRef coords[5];
+ unsigned chan;
/* WriteMask */
/* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
@@ -801,27 +804,22 @@ static void tex_fetch_args(
/* Coordinates */
/* XXX: Not all sample instructions need 4 address arguments. */
- if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
- LLVMValueRef src_w;
- unsigned chan;
- LLVMValueRef coords[4];
-
- emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
- src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
-
- for (chan = 0; chan < 3; chan++ ) {
- LLVMValueRef arg = lp_build_emit_fetch(bld_base,
- emit_data->inst, 0, chan);
+ if (inst->Instruction.Opcode == TGSI_OPCODE_TXP)
+ coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W)
+;
+
+ for (chan = 0; chan < 3; chan++ ) {
+ coords[chan] = lp_build_emit_fetch(bld_base,
+ emit_data->inst, 0,
+ chan);
+ if (inst->Instruction.Opcode == TGSI_OPCODE_TXP)
coords[chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_DIV,
- arg, src_w);
- }
- coords[3] = bld_base->base.one;
- emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm,
- coords, 4);
- } else
- emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
- 0, LP_CHAN_ALL);
+ coords[chan],
+ coords[3]);
+ }
+
+ coords[3] = bld_base->base.one;
if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
@@ -831,15 +829,24 @@ static void tex_fetch_args(
* That operand should be passed as a float value in the args array
* right after the coord vector. After packing it's not used anymore,
* that's why arg_count is not increased */
- emit_data->args[2] = lp_build_emit_fetch(bld_base, inst, 1, 0);
+ coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
}
if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
- radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, 1);
+ radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
}
+ for (chan = 0; chan < 4; chan++ ) {
+ coords[chan] = LLVMBuildBitCast(gallivm->builder,
+ coords[chan],
+ LLVMInt32TypeInContext(gallivm->context),
+ "");
+ }
+
+ emit_data->args[1] = lp_build_gather_values(gallivm, coords, 4);
+
/* Resource */
ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V8I32, SI_SGPR_RESOURCE);
offset = lp_build_const_int32(bld_base->base.gallivm,
@@ -869,19 +876,19 @@ static void tex_fetch_args(
static const struct lp_build_tgsi_action tex_action = {
.fetch_args = tex_fetch_args,
.emit = lp_build_tgsi_intrinsic,
- .intr_name = "llvm.SI.sample"
+ .intr_name = "llvm.SI.sample."
};
static const struct lp_build_tgsi_action txb_action = {
.fetch_args = tex_fetch_args,
.emit = lp_build_tgsi_intrinsic,
- .intr_name = "llvm.SI.sample.bias"
+ .intr_name = "llvm.SI.sampleb."
};
static const struct lp_build_tgsi_action txl_action = {
.fetch_args = tex_fetch_args,
.emit = lp_build_tgsi_intrinsic,
- .intr_name = "llvm.SI.sample.lod"
+ .intr_name = "llvm.SI.samplel."
};
commit b127ad34896f40f28ce792060ece23d75b0a5203
Author: Marek Olšák <maraeo@gmail.com>
Date: Tue Jan 29 15:55:10 2013 +0100
mesa: don't expose IBM_rasterpos_clip in a core context
glRasterPos doesn't exist in the core profile.
NOTE: This is a candidate for the stable branches (9.0 and 9.1).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit cc5fdaf2dce4465b09653f4bf3113674fb346646)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 7ae07fb..9f125b8 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -297,7 +297,7 @@ static const struct extension extension_table[] = {
{ "GL_ATI_texture_float", o(ARB_texture_float), GL, 2002 },
{ "GL_ATI_texture_mirror_once", o(ATI_texture_mirror_once), GL, 2006 },
{ "GL_IBM_multimode_draw_arrays", o(dummy_true), GL, 1998 },
- { "GL_IBM_rasterpos_clip", o(dummy_true), GL, 1996 },
+ { "GL_IBM_rasterpos_clip", o(dummy_true), GLL, 1996 },
{ "GL_IBM_texture_mirrored_repeat", o(dummy_true), GLL, 1998 },
{ "GL_INGR_blend_func_separate", o(EXT_blend_func_separate), GLL, 1999 },
{ "GL_MESA_pack_invert", o(MESA_pack_invert), GL, 2002 },
commit 1003652a7f17dbe373783ba5033cd25c231eb120
Author: Marek Olšák <maraeo@gmail.com>
Date: Fri Feb 1 00:32:55 2013 +0100
r300g: always put MSAA resources in VRAM
This along with the latest drm-fixes branch should help with bad performance
of MSAA. Remember: Nx MSAA can't be more than N times slower (where N=2,4,6).
Anyway, I recommend at least 512 MB of VRAM for Full HD 6x MSAA.
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit a06f03d795153ce060d99aafb61d10c27a47efc1)
diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index 6816fd0..327dbac 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -978,9 +978,9 @@ r300_texture_create_object(struct r300_screen *rscreen,
tex->tex.microtile = microtile;
tex->tex.macrotile[0] = macrotile;
tex->tex.stride_in_bytes_override = stride_in_bytes_override;
- tex->domain = base->flags & R300_RESOURCE_FLAG_TRANSFER ?
- RADEON_DOMAIN_GTT :
- RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT;
+ tex->domain = base->flags & R300_RESOURCE_FLAG_TRANSFER ? RADEON_DOMAIN_GTT :
+ base->nr_samples > 1 ? RADEON_DOMAIN_VRAM :
+ RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT;
tex->buf = buffer;
r300_texture_desc_init(rscreen, tex, base);
commit 9d8a866db319421b63ef3784ae22e51a06c94803
Author: Jerome Glisse <jglisse@redhat.com>
Date: Tue Jan 29 12:52:17 2013 -0500
r600g: add cs memory usage accounting and limit it v3
We are now seing cs that can go over the vram+gtt size to avoid
failing flush early cs that goes over 70% (gtt+vram) usage. 70%
is use to allow some fragmentation.
The idea is to compute a gross estimate of memory requirement of
each draw call. After each draw call, memory will be precisely
accounted. So the uncertainty is only on the current draw call.
In practice this gave very good estimate (+/- 10% of the target
memory limit).
v2: Remove left over from testing version, remove useless NULL
checking. Improve commit message.
v3: Add comment to code on memory accounting precision
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 0a3861f..5dd8b13 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1668,6 +1668,8 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
surf = (struct r600_surface*)state->cbufs[i];
rtex = (struct r600_texture*)surf->base.texture;
+ r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
+
if (!surf->color_initialized) {
evergreen_init_color_surface(rctx, surf);
}
@@ -1699,6 +1701,8 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
+ r600_context_add_resource_size(ctx, state->zsbuf->texture);
+
if (!surf->depth_initialized) {
evergreen_init_depth_surface(rctx, surf);
}
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 23f488a..a89f230 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -359,6 +359,16 @@ out_err:
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
boolean count_draw_in)
{
+ if (!ctx->ws->cs_memory_below_limit(ctx->rings.gfx.cs, ctx->vram, ctx->gtt)) {
+ ctx->gtt = 0;
+ ctx->vram = 0;
+ ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
+ return;
+ }
+ /* all will be accounted once relocation are emited */
+ ctx->gtt = 0;
+ ctx->vram = 0;
+
/* The number of dwords we already used in the CS so far. */
num_dw += ctx->rings.gfx.cs->cdw;
@@ -784,6 +794,8 @@ void r600_begin_new_cs(struct r600_context *ctx)
ctx->pm4_dirty_cdwords = 0;
ctx->flags = 0;
+ ctx->gtt = 0;
+ ctx->vram = 0;
/* Begin a new CS. */
r600_emit_command_buffer(ctx->rings.gfx.cs, &ctx->start_cs_cmd);
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 3ff42d3..ec59c92 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -447,6 +447,10 @@ struct r600_context {
unsigned backend_mask;
unsigned max_db; /* for OQ */
+ /* current unaccounted memory usage */
+ uint64_t vram;
+ uint64_t gtt;
+
/* Miscellaneous state objects. */
void *custom_dsa_flush;
void *custom_blend_resolve;
@@ -998,4 +1002,28 @@ static INLINE unsigned u_max_layer(struct pipe_resource *r, unsigned level)
}
}
+static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_resource *rr = (struct r600_resource *)r;
+
+ if (r == NULL) {
+ return;
+ }
+
+ /*
+ * The idea is to compute a gross estimate of memory requirement of
+ * each draw call. After each draw call, memory will be precisely
+ * accounted. So the uncertainty is only on the current draw call.
+ * In practice this gave very good estimate (+/- 10% of the target
+ * memory limit).
+ */
+ if (rr->domains & RADEON_DOMAIN_GTT) {
+ rctx->gtt += rr->buf->size;
+ }
+ if (rr->domains & RADEON_DOMAIN_VRAM) {
+ rctx->vram += rr->buf->size;
+ }
+}
+
#endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index c0bc2a5..44cd00e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1544,6 +1544,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
surf = (struct r600_surface*)state->cbufs[i];
rtex = (struct r600_texture*)surf->base.texture;
+ r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
if (!surf->color_initialized || force_cmask_fmask) {
r600_init_color_surface(rctx, surf, force_cmask_fmask);
@@ -1576,6 +1577,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
+ r600_context_add_resource_size(ctx, state->zsbuf->texture);
+
if (!surf->depth_initialized) {
r600_init_depth_surface(rctx, surf);
}
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 9386f61..33200a6 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -479,7 +479,8 @@ static void r600_set_index_buffer(struct pipe_context *ctx,
if (ib) {
pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
- memcpy(&rctx->index_buffer, ib, sizeof(*ib));
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