[Git][xorg-team/lib/mesa][debian-unstable] 55 commits: docs: add sha256sum for 24.0.5

Timo Aaltonen pushed to branch debian-unstable at X Strike Force / lib / mesa

Commits:

976b75c8
by Eric Engestrom at 2024-04-10T21:28:48+01:00
```
docs: add sha256sum for 24.0.5
```

b255492a

by Yonggang Luo at 2024-04-21T22:01:10+02:00

compiler/spirv: vtn_add_printf_string support for handling OpBitcast

specifically, it's handling
         %48 = OpBitcast %_ptr_UniformConstant_uchar %_str
         %49 = OpBitcast %_ptr_UniformConstant_uchar %_str_1

; SPIR-V
; Version: 1.4
; Generator: Khronos SPIR-V Tools Linker; 0
; Bound: 53
; Schema: 0
               OpCapability Addresses
               OpCapability Kernel
               OpCapability Int64
               OpCapability Int8
          %1 = OpExtInstImport "OpenCL.std"
               OpMemoryModel Physical64 OpenCL
               OpEntryPoint Kernel %2 "main_test" %_str %_str_1
          %5 = OpString "kernel_arg_type.main_test.float*,uint*,"
          %6 = OpString "kernel_arg_type_qual.main_test.,,"
               OpSource OpenCL_C 102000
               OpName %_str ".str"
               OpName %_str_1 ".str.1"
               OpName %main_test "main_test"
               OpName %src "src"
               OpName %dest "dest"
               OpName %entry "entry"
               OpName %src_addr "src.addr"
               OpName %dest_addr "dest.addr"
               OpName %arrayidx "arrayidx"
               OpName %call "call"
               OpName %src_0 "src"
               OpName %dest_0 "dest"
               OpModuleProcessed "Linked by SPIR-V Tools Linker"
               OpDecorate %_str Constant
               OpDecorate %_str Alignment 1
               OpDecorate %_str_1 Constant
               OpDecorate %_str_1 Alignment 1
               OpDecorate %src Alignment 4
               OpDecorate %dest Alignment 4
               OpDecorate %src_addr Alignment 8
               OpDecorate %dest_addr Alignment 8
               OpDecorate %src_0 Alignment 4
               OpDecorate %dest_0 Alignment 4
      %ulong = OpTypeInt 64 0
      %uchar = OpTypeInt 8 0
       %uint = OpTypeInt 32 0
    %ulong_7 = OpConstant %ulong 7
   %uchar_37 = OpConstant %uchar 37
  %uchar_115 = OpConstant %uchar 115
   %uchar_58 = OpConstant %uchar 58
   %uchar_32 = OpConstant %uchar 32
  %uchar_102 = OpConstant %uchar 102
    %uchar_0 = OpConstant %uchar 0
    %ulong_5 = OpConstant %ulong 5
   %uchar_84 = OpConstant %uchar 84
  %uchar_101 = OpConstant %uchar 101
  %uchar_116 = OpConstant %uchar 116
    %ulong_0 = OpConstant %ulong 0
%_arr_uchar_ulong_7 = OpTypeArray %uchar %ulong_7
%_ptr_UniformConstant__arr_uchar_ulong_7 = OpTypePointer UniformConstant %_arr_uchar_ulong_7
%_arr_uchar_ulong_5 = OpTypeArray %uchar %ulong_5
%_ptr_UniformConstant__arr_uchar_ulong_5 = OpTypePointer UniformConstant %_arr_uchar_ulong_5
       %void = OpTypeVoid
      %float = OpTypeFloat 32
%_ptr_CrossWorkgroup_float = OpTypePointer CrossWorkgroup %float
%_ptr_CrossWorkgroup_uint = OpTypePointer CrossWorkgroup %uint
         %40 = OpTypeFunction %void %_ptr_CrossWorkgroup_float %_ptr_CrossWorkgroup_uint
%_ptr_Function__ptr_CrossWorkgroup_float = OpTypePointer Function %_ptr_CrossWorkgroup_float
%_ptr_Function__ptr_CrossWorkgroup_uint = OpTypePointer Function %_ptr_CrossWorkgroup_uint
%_ptr_UniformConstant_uchar = OpTypePointer UniformConstant %uchar
         %44 = OpConstantComposite %_arr_uchar_ulong_7 %uchar_37 %uchar_115 %uchar_58 %uchar_32 %uchar_37 %uchar_102 %uchar_0
       %_str = OpVariable %_ptr_UniformConstant__arr_uchar_ulong_7 UniformConstant %44
         %45 = OpConstantComposite %_arr_uchar_ulong_5 %uchar_84 %uchar_101 %uchar_115 %uchar_116 %uchar_0
     %_str_1 = OpVariable %_ptr_UniformConstant__arr_uchar_ulong_5 UniformConstant %45
  %main_test = OpFunction %void DontInline %40
        %src = "" %_ptr_CrossWorkgroup_float
       %dest = OpFunctionParameter %_ptr_CrossWorkgroup_uint
      %entry = OpLabel
   %src_addr = OpVariable %_ptr_Function__ptr_CrossWorkgroup_float Function
  %dest_addr = OpVariable %_ptr_Function__ptr_CrossWorkgroup_uint Function
               OpStore %src_addr %src Aligned 8
               OpStore %dest_addr %dest Aligned 8
         %46 = OpLoad %_ptr_CrossWorkgroup_float %src_addr Aligned 8
   %arrayidx = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_float %46 %ulong_0
         %47 = OpLoad %float %arrayidx Aligned 4
         %48 = OpBitcast %_ptr_UniformConstant_uchar %_str
         %49 = OpBitcast %_ptr_UniformConstant_uchar %_str_1
       %call = OpExtInst %uint %1 printf %48 %49 %47
         %50 = OpLoad %_ptr_CrossWorkgroup_uint %dest_addr Aligned 8
               OpStore %50 %call Aligned 4
               OpReturn
               OpFunctionEnd
          %2 = OpFunction %void DontInline %40
      %src_0 = OpFunctionParameter %_ptr_CrossWorkgroup_float
     %dest_0 = OpFunctionParameter %_ptr_CrossWorkgroup_uint
         %51 = OpLabel
         %52 = OpFunctionCall %void %main_test %src_0 %dest_0
               OpReturn
               OpFunctionEnd

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26775>
(cherry picked from commit 616c0cd06727e19039d88a405adb4987b0d84959)

d731bfcd

by Eric Engestrom at 2024-04-21T22:21:50+02:00

.pick_status.json: Update to 2bb102f020b3a5834d219ab474c6bcdd02f88d09

c73b6da5

by Jonathan Gray at 2024-04-21T22:21:50+02:00

intel/dev: update DG2 device names

Ref: https://ark.intel.com/content/www/us/en/ark/products/237549/intel-arc-a380e-graphics.html
Ref: https://ark.intel.com/content/www/us/en/ark/products/237552/intel-arc-a310e-graphics.html
Ref: https://ark.intel.com/content/www/us/en/ark/products/237550/intel-arc-a370e-graphics.html
Ref: https://ark.intel.com/content/www/us/en/ark/products/237551/intel-arc-a350e-graphics.html
Ref: https://github.com/intel/compute-runtime/blob/864f42116cf4b0f5a91699cfe099d0c9186ca45b/shared/source/dll/devices/devices_base.inl#L49
Fixes: c74a578c54e ("intel/dev: Add 0x56ba-0x56bd DG2 PCI IDs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28643>
(cherry picked from commit a02d8c811d2fc084e4a212b8fba847451040bc29)

9376ec8d

by Jonathan Gray at 2024-04-21T22:21:50+02:00

intel/dev: update DG2 device names

Ref: https://github.com/intel/compute-runtime/blob/864f42116cf4b0f5a91699cfe099d0c9186ca45b/shared/source/dll/devices/devices_base.inl#L53
Fixes: 98f3d072b42 ("intel/dev: Add 0x56be and 0x56bf DG2 PCI IDs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28643>
(cherry picked from commit fef9ad6f66c0967a291e0ea612b6e5e0c0d87f16)

658e3980

by Mike Blumenkrantz at 2024-04-21T22:21:50+02:00

lavapipe: don't clamp index buffer size for null index buffer draws

this should execute however many draws the user is trying to execute

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28656>
(cherry picked from commit a5a2bd29698ce875d1c101e36f798dfa32e93c11)

e01f71ad

by Sagar Ghuge at 2024-04-21T22:21:51+02:00

anv: Fix typo in DestinationAlphaBlendFactor value

Workaround states that if Destination Alpha Blend
Factor==BLENDFACTOR_ZERO, instead use BLENDFACTOR_CONST_ALPHA with the
constant alpha set to 0.

We had typo while setting the DestinationAlphaBlendFactor, use
BLENDFACTOR_CONST_ALPHA instead of BLENDFACTOR_CONST_COLOR.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28640>
(cherry picked from commit 7cc604ed1b5c7f9c06811458ddf0ac0f33412304)

dc3a8b54

by Jonathan Gray at 2024-04-21T22:21:51+02:00

intel/dev: 0x7d45 is mtl-u not mtl-h

Ref: https://ark.intel.com/content/www/us/en/ark/products/237327/intel-core-ultra-7-processor-155u-12m-cache-up-to-4-80-ghz.html
Ref: Core Ultra Processor Datasheet, Doc. No.: 792044, Rev.: 002
Fixes: 48ff68820e8 ("intel/dev: Enable MTL PCI ids")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27973>
(cherry picked from commit 094a0a2ccbdd97e98009b453731d88c43d244b31)

bc760378

by Mike Blumenkrantz at 2024-04-21T22:21:51+02:00

zink: block LA formats with srgb

this doesn't work correctly

fixes #7218

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28674>
(cherry picked from commit 934188c3ca7e2e18891cd2d24f0140e657f5b514)

2a82433d

by Georg Lehmann at 2024-04-21T22:21:51+02:00

aco: use v1 definition for v_interp_p1lv_f16

The result of the first interpolation step is always fp32.

Fixes: 1647e098e94 ("aco: implement 16-bit interp")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28435>
(cherry picked from commit 893ee883fe7f40383ac546452b895d70a0e76971)

8b496ec0

by Sagar Ghuge at 2024-04-21T22:21:51+02:00

anv: Use appropriate argument format for indirect draw

If index is specified we can use the DRAWINDEXED otherwise we can simply
use DRAW argument format.

v2: (Rohan & Lionel)
- Fix the aligned_stride check

Fixes: 6d4f43f0d6 ("anv: Emit EXECUTE_INDIRECT_DRAW when available")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28658>
(cherry picked from commit 0aa632b519b0ad774520e6f83869f2a7bb9fabed)

c4b6f6b4

by nyanmisaka at 2024-04-21T22:21:51+02:00

radeonsi/uvd_enc: update to use correct padding size

Update padding size calculation to use cropping.
Original method could result in 0 padding, which
generated unnessary noise in the encoding result.

Cc: mesa-stable
Fixes: mesa/mesa#9196

Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28369>
(cherry picked from commit 7d00b759f3932e071d62420938cf0f3797befd67)

052f4952

by Patrick Lerda at 2024-04-21T22:21:51+02:00

r300: fix r300_draw_elements() behavior

Indeed, the pointer processed by r300_upload_index_buffer() was not the right one.
This is the reason why "deqp-gles2 --deqp-case=dEQP-GLES2.functional.draw.draw_elements.indices.user_ptr.index_byte"
was failing (the logs are below). This change corrects this issue and makes the related deqp tests work properly.

This change considers that r300_upload_index_buffer() sets indexBuffer to NULL. The indexBuffer resource
should be properly freed once the buffer is processed. This is required to avoid another refcnt imbalance
(another kind of memory leak).

==9962==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60200000721f at pc 0x7fd57b54a9a0 bp 0x7fffd2c39290 sp 0x7fffd2c38a40
READ of size 30 at 0x60200000721f thread T0
    #0 0x7fd57b54a99f in __interceptor_memcpy (/usr/lib64/libasan.so.6.0.0+0x3c99f)
    #1 0x7fd570d10528 in u_upload_data ../src/gallium/auxiliary/util/u_upload_mgr.c:333
    #2 0x7fd57114142b in r300_upload_index_buffer ../src/gallium/drivers/r300/r300_screen_buffer.c:44
    #3 0x7fd57113943c in r300_draw_elements ../src/gallium/drivers/r300/r300_render.c:632
    #4 0x7fd57113bbc4 in r300_draw_vbo ../src/gallium/drivers/r300/r300_render.c:840
    #5 0x7fd570d212e2 in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1487
    #6 0x7fd56fceb873 in _mesa_validated_drawrangeelements ../src/mesa/main/draw.c:1709
    #7 0x7fd56fcf28c5 in _mesa_DrawElementsBaseVertex ../src/mesa/main/draw.c:1852

Fixes: 330d0607ed6 ("gallium: remove pipe_index_buffer and set_index_buffer")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28523>
(cherry picked from commit 2b6993cb71a86e15af7523e1e436f2722e509dc1)

62cba397

by Mike Blumenkrantz at 2024-04-21T22:21:51+02:00

llvmpipe: clamp 32bit query results to low 32 bits rather than MIN

this should be more consistent with hardware driver behavior

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28671>
(cherry picked from commit 129bebd519928296aa98b42b9d46292973821ec1)

431c00e3

by Mike Blumenkrantz at 2024-04-21T22:21:51+02:00

lavapipe: clamp 32bit query results to low 32 bits rather than MIN

this should be more consistent with hardware driver behavior

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28671>
(cherry picked from commit ede4e4aae36b664dbfa511e7d8960ab53816ffcd)

15e6d8b8

by Dave Airlie at 2024-04-21T22:21:51+02:00

egl/dri2: don't bind dri2 for zink

I'm not sure why zink would want dri2 here instead of kopper,
I'm sure it's some side effect of something else, let zink
use the kopper paths.

This fixes:
dEQP-GL45-ES3.info.vendor
on zink on nvk with GL cts using EGL.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Fixes: 12a47b84b738 ("egl/dri2: trigger drawable invalidation from surface queries for zink")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28707>
(cherry picked from commit 223aedfa5dba263101a91314186be80861dbd3cf)

a4639e86

by Konstantin Seurer at 2024-04-21T22:21:51+02:00

lavapipe: Handle multiple planes in GetDescriptorEXT

Fixes: a13a07d ("lavapipe: add descriptor sets bindings for planar images")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28697>
(cherry picked from commit 8f5fb4e0951b6fdfba9de40d8144250156f7cb77)

881f4d60

by Samuel Pitoiset at 2024-04-21T22:21:51+02:00

radv: add missing SQTT markers when an indirect indexed draw is used with DGC

Since DGC preprocessing for IBO is supported, the driver generates
an indexed indirect draw but SQTT markers were missing and this
introduced complete non-sense in RGP captures.

Fixes: e59a16bbb8f ("radv: use an indirect draw when IBO isn't updated as part of DGC")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28710>
(cherry picked from commit 4586451b2dde802ebe00d1410b30a8772b8afde0)

b0c7292d

by Samuel Pitoiset at 2024-04-21T22:24:02+02:00

radv: use canonicalized VA for VM fault reports

Otherwise, the returned VA from vkGetBufferDeviceAddress() or via
VK_EXT_device_address_binding_report doesn't match and applications
would have to mask out.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28652>
(cherry picked from commit 7f608fc206e8f6ad0d4fdf7992ac211d9f64144e)

5e2893ba

by Mike Blumenkrantz at 2024-04-21T22:24:04+02:00

nir/remove_unused_io_vars: check all components to determine variable liveness

this otherwise only checked the first component

cc: mesa-stable

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28751>
(cherry picked from commit 98ce4a98ae734ac613cb078121520c48a5a94e10)

4c4b655c

by Paulo Zanoni at 2024-04-22T09:57:42+02:00

anv/sparse: replace device->using_sparse with device->num_sparse_resources

The device->using_sparse variable is only used at cmd_buffer_barrier()
to decide if we need to apply the heavier-weight flushes that are only
applicable to sparse resources. The big problem here is that we need
to apply the flushes to the non-image and non-buffer memory barriers,
so we were trying to limit those only to applications that ever submit
a sparse resource to the sparse queue.

The reason why we were applying this only to devices that ever
submitted sparse resources is that dxvk games have this thing where
during startup they create and then delete tiny sparse resources, so
switching device->using_sparse to true at resource creation would make
basically every dxvk game start applying the heavier-weight
workaround.

The problem with all that is that even if an application creates a
sparse resource but doesn't ever bind them, the resource should still
behave as an unbound resource (because they are bound with a NULL
bind), so the flushes affecting them should happen. This case is
exercised by vkd3d-proton/test_buffer_feedback_instructions_sm51.

In order to satisfy all the above cases and only really apply the
heavier-weight flushes to applications actually using sparse
resources, let's just count the number of sparse resources that
currently exist and then apply the workaround only if it's not zero.
That covers the dxvk case since dxvk deletes the resources as soon as
they create, so num_sparse_resources goes back to 0.

Testcase: vkd3d-proton/test_buffer_feedback_instructions_sm51
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10960
Fixes: 6368c1445f44 ("anv/sparse: add the initial code for Sparse Resources")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28724>
(cherry picked from commit 95dc34cd97a9cf909267a1c0fd625c8b5dc0a5ba)

062a7642

by Jose Maria Casanova Crespo at 2024-04-22T09:57:42+02:00

broadcom/compiler: needs_quad_helper_invocation enable PER_QUAD TMU access

We take advantage of the needs_quad_helper_invocation information to
only enable the PER_QUAD TMU access on Fragment Shaders when it is needed.

PER_QUAD access is also disabled on stages different to fragment shader.
Being enabled was causing MMU errors when TMU was doing indexed by vertexid
reads on disabled lanes on vertex stage. This problem was exercised by some
shaders from the GTK new GSK_RENDERER=ngl that were accessing a constant buffer
offset[6], but having PER_QUAD enabled on the TMU access by VertexID was
doing hidden incorrect access to not existing vertex 6 and 7 as TMU was
accessing the full quad.

cc: mesa-stable

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28740>
(cherry picked from commit 97f5721bfc4bbbce5c3a39cf48eeb6ad1fb9cf97)

7afd8e49

by Eric R. Smith at 2024-04-22T09:57:42+02:00

panfrost: fix a GPU/CPU synchronization problem

Remove a premature optimization. When PIPE_MAP_DISCARD_WHOLE_RESOURCE
is set we were setting create_new_bo, and then if that was set we skipped
a set of tests which if passed would cause a panfrost_flush_writer.

In fact we need that flush in some cases (e.g. when any batch is
reading the resource). Moreover, we should sometimes copy the resource
(set the copy_resource flag) and that again was being skipped if
create_new_bo was initially true due to PIPE_MAP_DISCARD_WHOLE_RESOURCE
being set.

Cc: mesa-stable
Signed-off-by: Eric R. Smith <eric.smith@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28406>
(cherry picked from commit e3d123b7a67aff618720e0bc550b2d27b1e56fc5)

68343412

by Eric R. Smith at 2024-04-22T09:57:42+02:00

panfrost: mark separate_stencil as valid when surface is valid

panfrost_initialize_surface is called when a surface is written to,
and marks that surface as valid. If the surface is a depth buffer
with a separate stencil, that separate stencil should also be marked
as valid; otherwise, readpixel will skip reading it (and hence the
stencil data will be read as uninitialized). This only affects
DEPTH32F_STENCIL8 formats.

Cc: mesa-stable
Signed-off-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28738>
(cherry picked from commit c939111f3fc545bf301d67c46fedc4c73a2c2c2b)

c9429bce

by Stéphane Cerveau at 2024-04-22T09:57:42+02:00

vulkan/video: hevc: b-frames can be reference or not

b-frames can be considered as reference, so the NAL type
should refer to reference type and either RASL or TRAIL
depending on the irap_pic_flag.

Fixes: 72f52329c ("vulkan/video: add a nal_unit lookup for hevc")

Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28657>
(cherry picked from commit 363a90d0c45cfc25fba6f8e59e6c53fb610846e8)

51dd480f

by Mike Blumenkrantz at 2024-04-22T09:57:42+02:00

lavapipe: disable stencil test if no stencil attachment

stencil test must not be enabled if there is no stencil attachment

fixes dEQP-VK.pipeline.*.stencil.no_stencil_att.dynamic_rendering.*

fixes #10990

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28772>
(cherry picked from commit fc691d9f37105e8da7aff45036a5ad1397d945cf)

5a1d9cb4

by Patrick Lerda at 2024-04-22T09:57:42+02:00

panfrost: remove panfrost_create_shader_state() related dead code

The pointer "xfb" is allocated with a clone of "so->nir" and lost
without further processing.

The function panfrost_shader_compile() was the one processing "xfb".
The call of this function was removed with the commit 40372bd720fe.
This makes "xfb" not required anymore.

For instance, this issue is triggered on a Mali-T820 with
"piglit/bin/arb_transform_feedback2-change-objects-while-paused -auto":
Indirect leak of 32776 byte(s) in 1 object(s) allocated from:
    #0 0xf78f30a6 in malloc (/usr/lib/libasan.so.6+0x840a6)
    #1 0xee9cd4ee in ralloc_size ../src/util/ralloc.c:118
    #2 0xee9cf7ae in create_slab ../src/util/ralloc.c:801
    #3 0xee9cf7ae in gc_alloc_size ../src/util/ralloc.c:840
    #4 0xef74ab82 in nir_undef_instr_create ../src/compiler/nir/nir.c:888
    #5 0xef76212c in clone_ssa_undef ../src/compiler/nir/nir_clone.c:328
    #6 0xef76212c in clone_instr ../src/compiler/nir/nir_clone.c:438
    #7 0xef7642d8 in clone_block ../src/compiler/nir/nir_clone.c:501
    #8 0xef7642d8 in clone_cf_list ../src/compiler/nir/nir_clone.c:555
    #9 0xef7657dc in clone_function_impl ../src/compiler/nir/nir_clone.c:632
    #10 0xef766cb8 in nir_shader_clone ../src/compiler/nir/nir_clone.c:743
    #11 0xf007673e in panfrost_create_shader_state ../src/gallium/drivers/panfrost/pan_shader.c:434
    #12 0xeeb6766c in st_create_common_variant ../src/mesa/state_tracker/st_program.c:781
    #13 0xeeb71d1c in st_get_common_variant ../src/mesa/state_tracker/st_program.c:834
    #14 0xeeb72ea2 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:1320
    #15 0xeeb72ea2 in st_finalize_program ../src/mesa/state_tracker/st_program.c:1421
    #16 0xef3806ec in st_link_glsl_to_nir ../src/mesa/state_tracker/st_glsl_to_nir.cpp:748
    #17 0xef3806ec in st_link_shader ../src/mesa/state_tracker/st_glsl_to_nir.cpp:984
    #18 0xef2992f6 in link_program ../src/mesa/main/shaderapi.c:1336
    #19 0xef2992f6 in link_program_error ../src/mesa/main/shaderapi.c:1445

Fixes: 40372bd720fe ("panfrost: Implement a disk cache")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28743>
(cherry picked from commit 4f5e9a21c5d10c3f3c5521ee5ad5757dade0de05)

39e103e1

by Mike Blumenkrantz at 2024-04-22T09:57:42+02:00

egl: fix defines for zink's dri3 check

if mesa is built without dri3 then dri3 should/can not be checked

cc: mesa-stable

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28570>
(cherry picked from commit ff37271ea73500d832538f52152095f63167fa9f)

28cd577d

by Mike Blumenkrantz at 2024-04-22T09:57:42+02:00

egl/android: fix zink loading

should be as simple as checking whether zink is being used

cc: mesa-stable

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28570>
(cherry picked from commit 6f13b201ade86cf6baa341fd37f9ac4bfb96a763)

6ba5ef79